SPI_HOST Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	2.083m	16.035ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	67.293us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	15.711us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	122.138us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	34.014us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	25.736us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	15.711us	1	1	100.00
		spi_host_csr_aliasing	4.000s	34.014us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	15.125us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	21.876us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	33.115us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	156.214us	1	1	100.00
		spi_host_error_cmd	4.000s	26.977us	1	1	100.00
		spi_host_event	7.000s	1.583ms	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	501.811us	1	1	100.00
V2	speed	spi_host_speed	7.000s	501.811us	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	501.811us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	1.167m	4.155ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	699.216us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	501.811us	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	501.811us	1	1	100.00
V2	duplex	spi_host_smoke	2.083m	16.035ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	2.083m	16.035ms	1	1	100.00
V2	stress_all	spi_host_stress_all	32.000s	4.530ms	1	1	100.00
V2	spien	spi_host_spien	8.000s	3.029ms	1	1	100.00
V2	stall	spi_host_status_stall	6.000s	179.660us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	115.010us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	156.214us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	16.947us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	20.328us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	161.681us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	161.681us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	67.293us	1	1	100.00
		spi_host_csr_rw	4.000s	15.711us	1	1	100.00
		spi_host_csr_aliasing	4.000s	34.014us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	111.648us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	67.293us	1	1	100.00
		spi_host_csr_rw	4.000s	15.711us	1	1	100.00
		spi_host_csr_aliasing	4.000s	34.014us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	111.648us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	187.594us	1	1	100.00
		spi_host_sec_cm	4.000s	83.832us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	187.594us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	29.817m	100.005ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.62633763467613364781975718849638934681701326997012602343684995634962356646848
      Line 150, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100004535153 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x82623d94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100004535153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---