SRAM_CTRL/MAIN Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	17.190s	416.223us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	24.008us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.480s	19.416us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.340s	452.239us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.500s	21.797us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.580s	1.880ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.480s	19.416us	1	1	100.00
		sram_ctrl_csr_aliasing	1.500s	21.797us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.978m	7.305ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.012m	2.728ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	10.505m	18.465ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.762m	3.135ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	19.553m	23.979ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	10.287m	50.952ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	38.430s	18.533ms	1	1	100.00
V2	executable	sram_ctrl_executable	3.642m	5.863ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.010s	520.245us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.256m	19.268ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	10.430s	3.472ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	44.250s	3.728ms	1	1	100.00
		sram_ctrl_throughput_w_readback	6.410s	692.650us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.736m	147.928ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.220s	448.066us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.192m	48.335ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.560s	12.981us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.590s	148.079us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.590s	148.079us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	24.008us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	19.416us	1	1	100.00
		sram_ctrl_csr_aliasing	1.500s	21.797us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.870s	26.187us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	24.008us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	19.416us	1	1	100.00
		sram_ctrl_csr_aliasing	1.500s	21.797us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.870s	26.187us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	20.880s	3.757ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.650s	7.512us	0	1	0.00
		sram_ctrl_tl_intg_err	1.990s	270.105us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.650s	7.512us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.990s	270.105us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.736m	147.928ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.736m	147.928ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.480s	19.416us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.642m	5.863ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.642m	5.863ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.642m	5.863ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	38.430s	18.533ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.570s	13.283ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	20.880s	3.757ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.440s	2.892ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	17.190s	416.223us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	17.190s	416.223us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.642m	5.863ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.650s	7.512us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	38.430s	18.533ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.650s	7.512us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.650s	7.512us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	17.190s	416.223us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.650s	7.512us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.939m	28.514ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.68559796625362521109099055860136821806256494518680560017634979539431455529733
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   7512289 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   7512289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---