SRAM_CTRL/RET Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	4.430s	88.651us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.560s	20.824us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.640s	26.670us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.380s	201.667us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.570s	40.935us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.060s	35.201us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.640s	26.670us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	40.935us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.140s	1.142ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.010s	124.034us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.121m	4.805ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.486m	17.013ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	20.660s	1.669ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.790m	3.198ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.240s	1.664ms	1	1	100.00
V2	executable	sram_ctrl_executable	7.902m	98.883ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.270s	487.966us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.154m	11.810ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	24.640s	124.265us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	6.660s	71.329us	1	1	100.00
		sram_ctrl_throughput_w_readback	16.960s	347.383us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.487m	14.301ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.810s	55.593us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	18.997m	33.675ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.950s	32.886us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.470s	29.762us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.470s	29.762us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.560s	20.824us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	26.670us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	40.935us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.810s	170.610us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.560s	20.824us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	26.670us	1	1	100.00
		sram_ctrl_csr_aliasing	1.570s	40.935us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.810s	170.610us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.290s	210.541us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.550s	4.453us	0	1	0.00
		sram_ctrl_tl_intg_err	2.320s	370.711us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.550s	4.453us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.320s	370.711us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.487m	14.301ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.487m	14.301ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.640s	26.670us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.902m	98.883ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.902m	98.883ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.902m	98.883ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.240s	1.664ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.730s	159.402us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.290s	210.541us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.240s	35.723us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	4.430s	88.651us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	4.430s	88.651us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.902m	98.883ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.550s	4.453us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.240s	1.664ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.550s	4.453us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.550s	4.453us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	4.430s	88.651us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.550s	4.453us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	30.230s	12.546ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.22557845582322286818666787537737768774605154564220196717016966184387247039200
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   4452911 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   4452911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---