UART Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: 856cba6

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.170s	682.902us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.640s	22.285us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.450s	13.450us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.730s	64.969us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.650s	62.783us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.640s	58.293us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.450s	13.450us	1	1	100.00
		uart_csr_aliasing	1.650s	62.783us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	2.153m	66.410ms	1	1	100.00
V2	parity	uart_smoke	2.170s	682.902us	1	1	100.00
		uart_tx_rx	2.153m	66.410ms	1	1	100.00
V2	parity_error	uart_intr	21.240s	58.492ms	1	1	100.00
		uart_rx_parity_err	2.006m	101.643ms	1	1	100.00
V2	watermark	uart_tx_rx	2.153m	66.410ms	1	1	100.00
		uart_intr	21.240s	58.492ms	1	1	100.00
V2	fifo_full	uart_fifo_full	12.860s	111.847ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	22.290s	332.280ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	7.130s	51.560ms	1	1	100.00
V2	rx_frame_err	uart_intr	21.240s	58.492ms	1	1	100.00
V2	rx_break_err	uart_intr	21.240s	58.492ms	1	1	100.00
V2	rx_timeout	uart_intr	21.240s	58.492ms	1	1	100.00
V2	perf	uart_perf	13.593m	21.794ms	1	1	100.00
V2	sys_loopback	uart_loopback	7.600s	12.853ms	1	1	100.00
V2	line_loopback	uart_loopback	7.600s	12.853ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.113m	60.018ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.990s	3.186ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	4.330s	1.153ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.230s	2.554ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.890m	43.854ms	1	1	100.00
V2	stress_all	uart_stress_all	5.985m	1.007s	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	18.320us	1	1	100.00
V2	intr_test	uart_intr_test	1.620s	13.672us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.400s	118.600us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.400s	118.600us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.640s	22.285us	1	1	100.00
		uart_csr_rw	1.450s	13.450us	1	1	100.00
		uart_csr_aliasing	1.650s	62.783us	1	1	100.00
		uart_same_csr_outstanding	1.600s	27.348us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.640s	22.285us	1	1	100.00
		uart_csr_rw	1.450s	13.450us	1	1	100.00
		uart_csr_aliasing	1.650s	62.783us	1	1	100.00
		uart_same_csr_outstanding	1.600s	27.348us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.780s	133.470us	1	1	100.00
		uart_tl_intg_err	2.100s	175.506us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.100s	175.506us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	14.750s	6.392ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00