CHIP Simulation Results

Wednesday April 23 2025 17:02:10 UTC

GitHub Revision: `856cba6`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.233m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.233m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.381m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.296m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.127m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.187m	6.843ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.187m	6.843ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.187m	6.843ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.554m		0	1	0.00
		chip_sw_example_manufacturer	2.664m		0	1	0.00
		chip_sw_example_concurrency	4.838m	5.234ms	1	1	100.00
		chip_sw_uart_smoketest_signed	41.725s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	15.590s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.350s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.350s		0	1	0.00
V1	xbar_smoke	xbar_smoke	17.040s	51.173us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	48.513s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.107m	9.168ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.731m	4.418ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	42.066s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	23.069s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.096m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	55.489s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.040s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.040s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.192m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.003m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.217m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.217m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.432m	4.048ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.064m	5.478ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.385m	13.189ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.830s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	15.838s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	15.518m	21.863ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.202m	5.924ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.926m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.926m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.343s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.075s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.075s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.409s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.927m	5.771ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.133m	5.977ms	1	1	100.00
		chip_sw_aes_idle	3.291m	3.769ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.447m	4.259ms	1	1	100.00
		chip_sw_kmac_idle	3.705m	4.224ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.113s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.213s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	10.710s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.744s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	10.814s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.964s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.789s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.169s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.760s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.763s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.890s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	10.814s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.964s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.789s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.169s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.760s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.763s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.890s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.284s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.230s	10.380us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.280s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.700s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.830s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.034s		0	1	0.00
		chip_sw_clkmgr_jitter	4.522m	5.207ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.778m	5.211ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.725s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.620s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	45.420s	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	48.150s	10.160us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	48.090s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	50.410s	10.400us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	14.039s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.564s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.864s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.517s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	20.366m	14.238ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.452m	16.814ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.075s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.201s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.452m	16.814ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.946s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.063s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.196s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.094s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.787s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	20.366m	14.238ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.385m	13.189ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	18.210m	20.024ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.564m	8.949ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	12.871m	30.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.451m	5.373ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	20.366m	14.238ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.702s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.013s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	20.366m	14.238ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.784s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	12.871m	30.017ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.962s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.215s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.098s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.309s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.945s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.065s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.013s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	17.102s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.620m	7.254ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.222s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	33.351s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.486s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	23.888s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.139m	9.922ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.760m	12.158ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.109s		0	1	0.00
		chip_prim_tl_access	8.980m	11.812ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	10.814s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	10.964s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.789s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.169s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.760s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.763s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.890s		0	1	0.00
		chip_rv_dm_lc_disabled	15.518m	21.863ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.677m	3.702ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	48.230s	10.380us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.480m	4.103ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.291m	3.769ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.442m	5.224ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	46.280s	10.220us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.447m	4.259ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.885m	4.817ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.534m	3.376ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	49.830s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.139m	9.922ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	38.230s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.728m	4.706ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.705m	4.224ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.249s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.249s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.458s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.859m	6.071ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.076s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.139m	9.922ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.700s	10.400us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	13.701s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.284s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.133m	5.977ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.133m	5.977ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.133m	5.977ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.777m	6.690ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.760m	12.158ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.760m	12.158ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.511m	7.053ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.034s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.109s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	20.366m	14.238ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.217m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.777m	6.690ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.139m	9.922ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.511m	7.053ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.558m	5.484ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.777m	6.690ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.139m	9.922ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.511m	7.053ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.558m	5.484ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.446s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	17.102s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.222s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	33.351s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	16.486s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	23.888s		0	1	0.00
		chip_sw_lc_ctrl_transition	14.103s		0	1	0.00
		chip_prim_tl_access	8.980m	11.812ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.980m	11.812ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.345s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	14.385s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.564s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.284s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.230s	10.380us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	46.280s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.700s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.830s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.034s		0	1	0.00
		chip_sw_clkmgr_jitter	4.522m	5.207ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.329m	8.974ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.329m	8.974ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.151m	5.714ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.737m	4.926ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.446m	3.323ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.622m	6.834ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.709m	5.014ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.983m	5.753ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.558m	5.484ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	18.210m	20.024ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	18.210m	20.024ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.481m	5.033ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.975m	4.775ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.678m	5.194ms	1	1	100.00
		chip_sw_csrng_smoketest	3.701m	4.087ms	1	1	100.00
		chip_sw_gpio_smoketest	3.817m	3.741ms	1	1	100.00
		chip_sw_hmac_smoketest	3.992m	4.694ms	1	1	100.00
		chip_sw_kmac_smoketest	4.051m	4.762ms	1	1	100.00
		chip_sw_otbn_smoketest	4.577m	5.499ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.456m	3.990ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.556m	3.524ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.883m	6.196ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.836m	4.975ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.284m	4.864ms	1	1	100.00
		chip_sw_uart_smoketest	3.192m	3.529ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	36.722s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	41.725s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	48.513s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.365s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.076m	4.632ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.109m	5.266ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.644m	3.366ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.400m	4.994ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	12.774s		0	1	0.00
		chip_rv_dm_lc_disabled	15.518m	21.863ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.803s		0	1	0.00
		chip_sw_lc_walkthrough_prod	16.456s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	18.372s		0	1	0.00
		chip_sw_lc_walkthrough_rma	50.542s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	12.774s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	21.759s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	25.290s		0	1	0.00
		rom_volatile_raw_unlock	10.416s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.698s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.566m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.923m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.342m	4.284ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.342m	4.284ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.350s		0	1	0.00
		chip_same_csr_outstanding	14.260s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.350s		0	1	0.00
		chip_same_csr_outstanding	14.260s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.298m	409.609us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	11.190s	11.700us	1	1	100.00
		xbar_smoke_large_delays	4.474m	2.377ms	1	1	100.00
		xbar_smoke_slow_rsp	4.801m	1.829ms	1	1	100.00
		xbar_random_zero_delays	1.331m	77.361us	1	1	100.00
		xbar_random_large_delays	12.754m	6.658ms	1	1	100.00
		xbar_random_slow_rsp	11.343m	4.176ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	21.120s	41.117us	1	1	100.00
		xbar_error_and_unmapped_addr	51.080s	115.664us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	21.150s	23.359us	1	1	100.00
		xbar_error_and_unmapped_addr	51.080s	115.664us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.565m	568.266us	1	1	100.00
		xbar_access_same_device_slow_rsp	37.843m	14.725ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.397m	205.244us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.617m	70.238us	1	1	100.00
		xbar_stress_all_with_error	5.689m	380.768us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	28.420m	981.820us	1	1	100.00
		xbar_stress_all_with_reset_error	19.128m	1.055ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.056s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.884s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.032s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.712s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.068s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.948s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.310s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.101s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.182s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.804s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.297s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.580s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.507s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	13.330s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.398s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.260s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.369s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.422s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	14.123s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	13.671s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.856s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.938s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.197s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.989s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.574s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.093s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.058s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.441s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.531s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.264s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.927s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.982s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.773s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.748s		0	1	0.00
		rom_e2e_asm_init_dev	11.781s		0	1	0.00
		rom_e2e_asm_init_prod	11.023s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.057s		0	1	0.00
		rom_e2e_asm_init_rma	11.310s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.165s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.546s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.439s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.750s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.424m	4.551ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.323m	4.293ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.804s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.156s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.316s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	15.054s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	20.366m	14.238ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	17.839s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.087m	16.418ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.685s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.290s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.804s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.156s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.316s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.769s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.599s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.606s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	58.885s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	18.085m	15.668ms	1	1	100.00
		chip_plic_all_irqs_0	9.632m	6.005ms	1	1	100.00
		chip_plic_all_irqs_10	10.231m	7.488ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.514m	5.955ms	1	1	100.00
		chip_sw_dma_abort	4.436m	4.606ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.745s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.509s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.433s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.795s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.719s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.719s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.152s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.330s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.336s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.130s		0	1	0.00
		chip_sw_mbx_smoketest	4.053m	4.696ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.30907653280023718831961513464320895153425659306628575007627094261467025074286
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (33daa3)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (b6363d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 73.015s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.7347680640303920755188043593749540341815086839449602328370931835448302486719
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (71ae75)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 142.187s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.59828900712183452217502974311047478282467124077445362917000705430584810725338
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (4bacec)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 122.724s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.10261269139073049146199123514238292649911734673160772932069681564913004791535
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (1decdc)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 121.202s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.105044784483515086122197931991557051348528651139487142598219830252803912092304
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (940579)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 49.146s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.75785264809111178563595993687574168456361495122231946684830736538112936664036
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.61028528965618672490902442082311913980611135315553104461486330132389641921718
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.85580279405349180978490184402918946848243507078610808524954462096075704720702
    Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.96209654499368388347907865721099542441404548698409230526514236991939272206074
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.22100644155288126736475518342109923625105238603011270445182858119686561781982
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.47502445680277467476241811747320190336910002793378497088601613970415063258319
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.21887298127173269189431081456352396943345797176250839327355922218071738907360
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.15061983329275311799620813311922737033154913864564787139327642470908763142218
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 2 failures:
- Test chip_sw_rstmgr_cpu_info has 1 failures.
  - 0.chip_sw_rstmgr_cpu_info.52949682805182063585742668556388648963306958021788966674826728363907581342834
    Line 475, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
```
  UVM_ERROR @ 20023.882216 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20023.882216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_irq has 1 failures.
  - 0.chip_sw_aon_timer_irq.49040666510050050708773275989363457326395682054700817326199169438354800429598
    Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
```
  UVM_ERROR @ 18017.892988 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.892988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.69327143133604160394870308424511383336815536199457446878570425942036981226689
Line 490, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9922.400344 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (75196750019652682908756456366444596735173791081637574661260136257108053014975 [0xa63fda2cd893975daa8e7bf2429e622f061845a22af5a25a6e59a22c864f39bf] vs 2213572788116230312738852598897149647367501761813858413568837834494553715632 [0x4e4d67a01ba628384ed195931d0283e50530a600349c63fb7f4c410d47173b0])
  UVM_INFO @ 9922.400344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.111125351701413357088422599352238738588461781006484733308634324959810707134259
Line 489, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7254.323900 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (34795511539842613633622483739561064600710304754172457466196145157885670569253 [0x4ced8fc632f14080aa794ec4ba2fadefe399eb0a3fdfd16afee33f60248db525] vs 67452443952877974951586687002309040844034092232269231361227354121489953662742 [0x9520baf7e39e61e5d0c48a28c753227b833c3ad2613f05f5a34d3160dc512716])
  UVM_INFO @ 7254.323900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.111789391825825084241488698887254638879135079131626849340486783188854507737783
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4048.092375 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hbbc9b9ba  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h1  a_user: 'h248b2  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4048.092375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.28050940420383782284736686997112184993413071483482508773604865911658178677239
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5477.917153 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hd6753aa6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h0  a_user: 'h2692c  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5477.917153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.83191634751477128371143843701906432460000498246688953076281402018548817302024
    Line 501, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4417.620160 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4417.620160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.90133419128308823515031807028401485094356555298824967570139472280040804737813
    Line 454, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 30016.971119 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 30000000 ns

  UVM_INFO @ 30016.971119 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.28332938176148020558080739174297974815782258687581131407327569735060597289963
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5714.222756 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5714.222756 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.26848675304432721201734863560511790501060758664758012860964262044571077953464
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6833.986760 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6833.986760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.78937879748373798431337832438698577517585394250260547768911352159496213214997
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.14049798188219834312509069248322934236490730493741467020248536805437459708257
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4284.340340 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4284.340340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.60266237405341702027278035427867980617051244104234322453202163654170755289981
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13188.839528 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13188.839528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.36490492012058600593241370485102137672149781198708117523563433191388135620111
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.56840087648480717004761451343778779176001200061210143253534570255725814729252
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4605.527304 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4605.527304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```