DMA Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	327.095us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	808.381us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	1.196ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	40.347us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	16.750us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	547.715us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	2.496ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	74.952us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	16.750us	1	1	100.00
		dma_csr_aliasing	9.000s	2.496ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.317m	5.905ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	40.350m	4.412s	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	25.900m	164.557ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	5.600m	33.446ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	40.350m	4.412s	1	1	100.00
V2	dma_abort	dma_abort	18.000s	1.308ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	54.000s	17.359ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	74.265us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	733.299us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	733.299us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	40.347us	1	1	100.00
		dma_csr_rw	4.000s	16.750us	1	1	100.00
		dma_csr_aliasing	9.000s	2.496ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	114.249us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	40.347us	1	1	100.00
		dma_csr_rw	4.000s	16.750us	1	1	100.00
		dma_csr_aliasing	9.000s	2.496ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	114.249us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	36.000s	97.058us	1	1	100.00
		dma_generic_stress	5.600m	33.446ms	1	1	100.00
		dma_handshake_stress	40.350m	4.412s	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	798.223us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.783m	12.226ms	1	1	100.00
		dma_longer_transfer	6.000s	706.993us	1	1	100.00
		TOTAL			21	21	100.00