EDN Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.980s 114.489us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.650s 37.748us 1 1 100.00
V1 csr_rw edn_csr_rw 2.350s 15.461us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 7.190s 225.372us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.140s 32.204us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.990s 63.381us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.350s 15.461us 1 1 100.00
edn_csr_aliasing 2.140s 32.204us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.060s 39.719us 1 1 100.00
V2 csrng_commands edn_genbits 2.060s 39.719us 1 1 100.00
V2 genbits edn_genbits 2.060s 39.719us 1 1 100.00
V2 interrupts edn_intr 1.770s 26.750us 1 1 100.00
V2 alerts edn_alert 2.190s 29.872us 1 1 100.00
V2 errs edn_err 2.040s 29.162us 1 1 100.00
V2 disable edn_disable 1.680s 30.293us 1 1 100.00
edn_disable_auto_req_mode 2.150s 314.106us 1 1 100.00
V2 stress_all edn_stress_all 2.410s 279.143us 1 1 100.00
V2 intr_test edn_intr_test 1.710s 15.592us 1 1 100.00
V2 alert_test edn_alert_test 1.740s 15.423us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.010s 98.847us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.010s 98.847us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.650s 37.748us 1 1 100.00
edn_csr_rw 2.350s 15.461us 1 1 100.00
edn_csr_aliasing 2.140s 32.204us 1 1 100.00
edn_same_csr_outstanding 2.220s 123.895us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.650s 37.748us 1 1 100.00
edn_csr_rw 2.350s 15.461us 1 1 100.00
edn_csr_aliasing 2.140s 32.204us 1 1 100.00
edn_same_csr_outstanding 2.220s 123.895us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.910s 1.718ms 1 1 100.00
edn_tl_intg_err 3.770s 98.388us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.810s 50.917us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.190s 29.872us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.910s 1.718ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.910s 1.718ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.910s 1.718ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.910s 1.718ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.190s 29.872us 1 1 100.00
edn_sec_cm 4.910s 1.718ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.190s 29.872us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.770s 98.388us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets