HMAC Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 5.250s 116.679us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.650s 27.087us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.690s 30.277us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 7.290s 858.299us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 4.460s 904.463us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.930s 26.675us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.690s 30.277us 1 1 100.00
hmac_csr_aliasing 4.460s 904.463us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 57.850s 6.885ms 1 1 100.00
V2 back_pressure hmac_back_pressure 44.930s 2.016ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 3.194m 12.045ms 1 1 100.00
hmac_test_sha384_vectors 18.660s 486.907us 1 1 100.00
hmac_test_sha512_vectors 6.321m 26.285ms 1 1 100.00
hmac_test_hmac256_vectors 6.610s 205.024us 1 1 100.00
hmac_test_hmac384_vectors 7.450s 256.502us 1 1 100.00
hmac_test_hmac512_vectors 10.670s 1.376ms 1 1 100.00
V2 burst_wr hmac_burst_wr 7.810s 745.316us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 4.891m 2.581ms 1 1 100.00
V2 error hmac_error 49.680s 1.256ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 30.860s 18.478ms 1 1 100.00
V2 save_and_restore hmac_smoke 5.250s 116.679us 1 1 100.00
hmac_long_msg 57.850s 6.885ms 1 1 100.00
hmac_back_pressure 44.930s 2.016ms 1 1 100.00
hmac_datapath_stress 4.891m 2.581ms 1 1 100.00
hmac_burst_wr 7.810s 745.316us 1 1 100.00
hmac_stress_all 21.552m 84.132ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 5.250s 116.679us 1 1 100.00
hmac_long_msg 57.850s 6.885ms 1 1 100.00
hmac_back_pressure 44.930s 2.016ms 1 1 100.00
hmac_datapath_stress 4.891m 2.581ms 1 1 100.00
hmac_wipe_secret 30.860s 18.478ms 1 1 100.00
hmac_test_sha256_vectors 3.194m 12.045ms 1 1 100.00
hmac_test_sha384_vectors 18.660s 486.907us 1 1 100.00
hmac_test_sha512_vectors 6.321m 26.285ms 1 1 100.00
hmac_test_hmac256_vectors 6.610s 205.024us 1 1 100.00
hmac_test_hmac384_vectors 7.450s 256.502us 1 1 100.00
hmac_test_hmac512_vectors 10.670s 1.376ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 5.250s 116.679us 1 1 100.00
hmac_long_msg 57.850s 6.885ms 1 1 100.00
hmac_back_pressure 44.930s 2.016ms 1 1 100.00
hmac_datapath_stress 4.891m 2.581ms 1 1 100.00
hmac_burst_wr 7.810s 745.316us 1 1 100.00
hmac_error 49.680s 1.256ms 1 1 100.00
hmac_wipe_secret 30.860s 18.478ms 1 1 100.00
hmac_test_sha256_vectors 3.194m 12.045ms 1 1 100.00
hmac_test_sha384_vectors 18.660s 486.907us 1 1 100.00
hmac_test_sha512_vectors 6.321m 26.285ms 1 1 100.00
hmac_test_hmac256_vectors 6.610s 205.024us 1 1 100.00
hmac_test_hmac384_vectors 7.450s 256.502us 1 1 100.00
hmac_test_hmac512_vectors 10.670s 1.376ms 1 1 100.00
hmac_stress_all 21.552m 84.132ms 1 1 100.00
V2 stress_all hmac_stress_all 21.552m 84.132ms 1 1 100.00
V2 alert_test hmac_alert_test 1.380s 18.181us 1 1 100.00
V2 intr_test hmac_intr_test 1.510s 15.909us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.840s 526.688us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.840s 526.688us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.650s 27.087us 1 1 100.00
hmac_csr_rw 1.690s 30.277us 1 1 100.00
hmac_csr_aliasing 4.460s 904.463us 1 1 100.00
hmac_same_csr_outstanding 2.610s 49.830us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.650s 27.087us 1 1 100.00
hmac_csr_rw 1.690s 30.277us 1 1 100.00
hmac_csr_aliasing 4.460s 904.463us 1 1 100.00
hmac_same_csr_outstanding 2.610s 49.830us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.560s 74.481us 1 1 100.00
hmac_tl_intg_err 3.050s 106.152us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.050s 106.152us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 5.250s 116.679us 1 1 100.00
V3 stress_reset hmac_stress_reset 4.240s 760.202us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 13.440s 7.001ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.290s 43.170us 1 1 100.00
TOTAL 28 28 100.00