I2C Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: `0fa5019`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	14.260s	1.751ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	22.480s	1.027ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.540s	25.774us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.620s	49.450us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.150s	364.619us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.190s	69.442us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.700s	110.543us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.620s	49.450us	1	1	100.00
		i2c_csr_aliasing	2.190s	69.442us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.630s	266.152us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	8.341m	85.720ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	4.440s	1.079ms	1	1	100.00
V2	host_override	i2c_host_override	1.490s	52.762us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.986m	4.379ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	53.900s	6.034ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.800s	552.852us	1	1	100.00
		i2c_host_fifo_fmt_empty	13.080s	542.618us	1	1	100.00
		i2c_host_fifo_reset_rx	3.840s	205.183us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	34.860s	2.123ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	6.080s	3.775ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	3.870s	323.675us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.190s	13.618ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	1.196m	46.438ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.880s	1.073ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	14.480s	3.542ms	1	1	100.00
		i2c_target_intr_smoke	3.390s	593.721us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.960s	233.781us	1	1	100.00
		i2c_target_fifo_reset_tx	2.390s	280.133us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	9.172m	53.638ms	1	1	100.00
		i2c_target_stress_rd	14.480s	3.542ms	1	1	100.00
		i2c_target_intr_stress_wr	31.450s	20.386ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.510s	1.434ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	3.230s	3.327ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.070s	1.101ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.760s	297.393us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.240s	254.701us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.020s	886.267us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	4.440s	1.079ms	1	1	100.00
		i2c_host_perf_precise	1.880s	185.819us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	6.080s	3.775ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.020s	59.056us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.010s	1.017ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.510s	458.966us	1	1	100.00
		i2c_target_nack_txstretch	1.860s	264.156us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.140s	194.154us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.160s	2.515ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.430s	157.307us	1	1	100.00
V2	intr_test	i2c_intr_test	1.720s	17.663us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.450s	685.347us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.450s	685.347us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.540s	25.774us	1	1	100.00
		i2c_csr_rw	1.620s	49.450us	1	1	100.00
		i2c_csr_aliasing	2.190s	69.442us	1	1	100.00
		i2c_same_csr_outstanding	1.730s	63.179us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.540s	25.774us	1	1	100.00
		i2c_csr_rw	1.620s	49.450us	1	1	100.00
		i2c_csr_aliasing	2.190s	69.442us	1	1	100.00
		i2c_same_csr_outstanding	1.730s	63.179us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.450s	159.176us	1	1	100.00
		i2c_sec_cm	1.610s	45.999us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.450s	159.176us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	2.510s	1.204ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.090s	119.834us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.920s	1.729ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 2 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.33249824552661768637802959617424604413582540579214800069002974463113235764153
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 119833647 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 5 [0x5])
  UVM_INFO @ 119833647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.106898853601971136634167764616700911933764234175237502919391153364722805134642
    Line 94, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1728861607 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 16 [0x10])
  UVM_INFO @ 1728861607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.89104864622314127764690231444513493861319323613698766158161499764539806542083
    Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1204067310 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1204067310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.46902813285186195145523475413992685222542456800000532399095430897139344639154
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 323675012 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @23083