KEYMGR Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.960s	55.420us	1	1	100.00
V1	random	keymgr_random	3.110s	51.013us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.790s	19.039us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.920s	24.115us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	5.940s	509.913us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	7.650s	520.458us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.250s	219.411us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.920s	24.115us	1	1	100.00
		keymgr_csr_aliasing	7.650s	520.458us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	7.290s	367.693us	1	1	100.00
V2	sideload	keymgr_sideload	2.500s	33.091us	1	1	100.00
		keymgr_sideload_kmac	2.510s	67.816us	1	1	100.00
		keymgr_sideload_aes	4.090s	205.575us	1	1	100.00
		keymgr_sideload_otbn	3.340s	97.023us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	4.250s	803.927us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.280s	214.333us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.520s	372.621us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.990s	218.970us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	17.390s	3.992ms	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.270s	136.221us	1	1	100.00
V2	stress_all	keymgr_stress_all	33.390s	2.938ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.630s	33.086us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.580s	25.059us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.150s	360.505us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.150s	360.505us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.790s	19.039us	1	1	100.00
		keymgr_csr_rw	1.920s	24.115us	1	1	100.00
		keymgr_csr_aliasing	7.650s	520.458us	1	1	100.00
		keymgr_same_csr_outstanding	2.240s	50.144us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.790s	19.039us	1	1	100.00
		keymgr_csr_rw	1.920s	24.115us	1	1	100.00
		keymgr_csr_aliasing	7.650s	520.458us	1	1	100.00
		keymgr_same_csr_outstanding	2.240s	50.144us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
		keymgr_tl_intg_err	3.450s	507.166us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.750s	158.898us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.750s	158.898us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.750s	158.898us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.750s	158.898us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.810s	12.333us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.450s	507.166us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.750s	158.898us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	7.290s	367.693us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.110s	51.013us	1	1	100.00
		keymgr_csr_rw	1.920s	24.115us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.110s	51.013us	1	1	100.00
		keymgr_csr_rw	1.920s	24.115us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.110s	51.013us	1	1	100.00
		keymgr_csr_rw	1.920s	24.115us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.280s	214.333us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	17.390s	3.992ms	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	17.390s	3.992ms	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.110s	51.013us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.690s	149.452us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.640s	342.199us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.280s	214.333us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.640s	342.199us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.640s	342.199us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.640s	342.199us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.550s	303.445us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.640s	342.199us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	2.980s	481.955us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			28	30	93.33

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.72879202067496921023526180234007658591584911716760350457426755144550560477771
      Line 96, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 481954892 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 481954892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.43692763299472228263637761596121908061393839925475777975930979080228404722640
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
        UVM_ERROR @  12333413 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
        UVM_INFO @  12333413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---