KMAC/MASKED Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	13.940s	1.415ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.880s	43.450us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.610s	167.498us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.110s	157.690us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.090s	159.244us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.590s	117.995us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.610s	167.498us	1	1	100.00
		kmac_csr_aliasing	6.090s	159.244us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.570s	13.863us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.860s	107.910us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.190s	1.516ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.057m	3.570ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.800s	6.880ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.060s	2.216ms	1	1	100.00
		kmac_test_vectors_sha3_384	24.560s	2.143ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.770m	32.936ms	1	1	100.00
		kmac_test_vectors_shake_128	1.890m	4.087ms	1	1	100.00
		kmac_test_vectors_shake_256	5.187m	20.392ms	1	1	100.00
		kmac_test_vectors_kmac	3.650s	306.450us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.610s	253.205us	1	1	100.00
V2	sideload	kmac_sideload	4.819m	7.409ms	1	1	100.00
V2	app	kmac_app	3.276m	39.536ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.356m	12.839ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.838m	8.281ms	1	1	100.00
V2	error	kmac_error	4.541m	11.527ms	1	1	100.00
V2	key_error	kmac_key_error	3.590s	425.943us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	7.220s	1.257ms	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	30.460s	1.320ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.640s	19.235us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	38.400s	4.654ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	16.420s	2.064ms	1	1	100.00
V2	stress_all	kmac_stress_all	15.060m	53.501ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.920s	27.249us	1	1	100.00
V2	alert_test	kmac_alert_test	1.690s	40.137us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.150s	56.550us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.150s	56.550us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.880s	43.450us	1	1	100.00
		kmac_csr_rw	1.610s	167.498us	1	1	100.00
		kmac_csr_aliasing	6.090s	159.244us	1	1	100.00
		kmac_same_csr_outstanding	2.040s	40.194us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.880s	43.450us	1	1	100.00
		kmac_csr_rw	1.610s	167.498us	1	1	100.00
		kmac_csr_aliasing	6.090s	159.244us	1	1	100.00
		kmac_same_csr_outstanding	2.040s	40.194us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.270s	68.552us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.270s	68.552us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.270s	68.552us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.270s	68.552us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.540s	274.161us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	54.380s	43.450ms	1	1	100.00
		kmac_tl_intg_err	4.610s	938.473us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.610s	938.473us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	16.420s	2.064ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	13.940s	1.415ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.819m	7.409ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.270s	68.552us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	54.380s	43.450ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	54.380s	43.450ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	54.380s	43.450ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	13.940s	1.415ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	16.420s	2.064ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	54.380s	43.450ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	32.250s	786.101us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	13.940s	1.415ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.930s	45.954us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.94410290600407778657515973324498205803525656152568161865059272762294372298927
      Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  45953939 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
        UVM_INFO @  45953939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---