KMAC/UNMASKED Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	31.110s	1.454ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.970s	56.995us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.800s	20.395us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.340s	498.741us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.350s	249.473us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.880s	336.124us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.800s	20.395us	1	1	100.00
		kmac_csr_aliasing	4.350s	249.473us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.820s	16.763us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.920s	146.912us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	40.698m	123.007ms	1	1	100.00
V2	burst_write	kmac_burst_write	8.946m	38.827ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.442m	121.761ms	1	1	100.00
		kmac_test_vectors_sha3_256	18.179m	17.482ms	1	1	100.00
		kmac_test_vectors_sha3_384	20.830s	1.875ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.990s	957.216us	1	1	100.00
		kmac_test_vectors_shake_128	1.910m	15.601ms	1	1	100.00
		kmac_test_vectors_shake_256	1.224m	1.572ms	1	1	100.00
		kmac_test_vectors_kmac	2.980s	62.872us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.190s	1.373ms	1	1	100.00
V2	sideload	kmac_sideload	3.788m	4.317ms	1	1	100.00
V2	app	kmac_app	19.510s	1.437ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.803m	55.884ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.986m	18.157ms	1	1	100.00
V2	error	kmac_error	2.061m	2.711ms	1	1	100.00
V2	key_error	kmac_key_error	3.950s	2.019ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.740s	264.774us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	3.840s	180.769us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	9.410s	206.050us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	51.020s	15.840ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.340s	46.222us	1	1	100.00
V2	stress_all	kmac_stress_all	3.721m	67.118ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.640s	21.077us	1	1	100.00
V2	alert_test	kmac_alert_test	1.770s	35.856us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.480s	730.084us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.480s	730.084us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.970s	56.995us	1	1	100.00
		kmac_csr_rw	1.800s	20.395us	1	1	100.00
		kmac_csr_aliasing	4.350s	249.473us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	219.373us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.970s	56.995us	1	1	100.00
		kmac_csr_rw	1.800s	20.395us	1	1	100.00
		kmac_csr_aliasing	4.350s	249.473us	1	1	100.00
		kmac_same_csr_outstanding	2.150s	219.373us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.860s	30.866us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.860s	30.866us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.860s	30.866us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.860s	30.866us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.730s	90.188us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	55.110s	24.405ms	1	1	100.00
		kmac_tl_intg_err	1.670s	45.593us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.670s	45.593us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.340s	46.222us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	31.110s	1.454ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.788m	4.317ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.860s	30.866us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	55.110s	24.405ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	55.110s	24.405ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	55.110s	24.405ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	31.110s	1.454ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.340s	46.222us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	55.110s	24.405ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.571m	8.864ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	31.110s	1.454ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.963m	3.067ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.70997785395970188151488033387930378161858036560061257527870776079651582600487
      Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  45592638 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  45592638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---