OTBN Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 14.000s 372.110us 1 1 100.00
V1 single_binary otbn_single 10.000s 23.155us 1 1 100.00
V1 csr_hw_reset otbn_csr_hw_reset 6.000s 50.536us 1 1 100.00
V1 csr_rw otbn_csr_rw 6.000s 34.237us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 8.000s 181.819us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 37.376us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 11.000s 78.671us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 34.237us 1 1 100.00
otbn_csr_aliasing 6.000s 37.376us 1 1 100.00
V1 mem_walk otbn_mem_walk 28.000s 4.965ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 10.000s 265.400us 1 1 100.00
V1 TOTAL 9 9 100.00
V2 reset_recovery otbn_reset 17.000s 208.114us 1 1 100.00
V2 multi_error otbn_multi_err 45.000s 174.038us 1 1 100.00
V2 back_to_back otbn_multi 59.000s 420.224us 1 1 100.00
V2 stress_all otbn_stress_all 39.000s 1.147ms 1 1 100.00
V2 lc_escalation otbn_escalate 10.000s 43.705us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 41.235us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 11.000s 79.722us 1 1 100.00
V2 alert_test otbn_alert_test 8.000s 33.217us 1 1 100.00
V2 intr_test otbn_intr_test 6.000s 114.830us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 7.000s 155.857us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 7.000s 155.857us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 6.000s 50.536us 1 1 100.00
otbn_csr_rw 6.000s 34.237us 1 1 100.00
otbn_csr_aliasing 6.000s 37.376us 1 1 100.00
otbn_same_csr_outstanding 6.000s 13.418us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 6.000s 50.536us 1 1 100.00
otbn_csr_rw 6.000s 34.237us 1 1 100.00
otbn_csr_aliasing 6.000s 37.376us 1 1 100.00
otbn_same_csr_outstanding 6.000s 13.418us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S mem_integrity otbn_imem_err 11.000s 101.920us 1 1 100.00
otbn_dmem_err 10.000s 66.938us 1 1 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 10.000s 99.850us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 200.406us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 359.159us 1 1 100.00
otbn_urnd_err 7.000s 16.326us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 8.000s 55.479us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 10.000s 30.602us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 8.000s 26.769us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 2.650m 1.042ms 1 1 100.00
otbn_tl_intg_err 13.000s 61.895us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 23.000s 181.807us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 14.000s 372.110us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 10.000s 66.938us 1 1 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 11.000s 101.920us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 13.000s 61.895us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 10.000s 43.705us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 11.000s 101.920us 1 1 100.00
otbn_dmem_err 10.000s 66.938us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 41.235us 1 1 100.00
otbn_illegal_mem_acc 8.000s 55.479us 1 1 100.00
otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 10.000s 23.155us 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 11.000s 101.920us 1 1 100.00
otbn_dmem_err 10.000s 66.938us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 41.235us 1 1 100.00
otbn_illegal_mem_acc 8.000s 55.479us 1 1 100.00
otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 10.000s 43.705us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 11.000s 101.920us 1 1 100.00
otbn_dmem_err 10.000s 66.938us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 41.235us 1 1 100.00
otbn_illegal_mem_acc 8.000s 55.479us 1 1 100.00
otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 10.000s 23.155us 1 1 100.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 8.000s 16.595us 1 1 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 8.000s 22.177us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 28.000s 1.300ms 1 1 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 28.000s 1.300ms 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 9.000s 13.057us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 9.000s 122.404us 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 121.024us 1 1 100.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 9.000s 121.024us 1 1 100.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 7.000s 24.287us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 10.000s 23.155us 1 1 100.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 10.000s 23.155us 1 1 100.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 10.000s 23.155us 1 1 100.00
V2S sec_cm_write_mem_integrity otbn_multi 59.000s 420.224us 1 1 100.00
V2S sec_cm_ctrl_flow_count otbn_single 10.000s 23.155us 1 1 100.00
V2S sec_cm_ctrl_flow_sca otbn_single 10.000s 23.155us 1 1 100.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 9.000s 67.148us 1 1 100.00
V2S sec_cm_key_sideload otbn_single 10.000s 23.155us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 2.650m 1.042ms 1 1 100.00
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 2.000m 1.815ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 41 41 100.00