ROM_CTRL/64KB Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.570s 345.940us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.010s 800.558us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.760s 1.064ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.360s 2.501ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.450s 208.636us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.470s 218.797us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.760s 1.064ms 1 1 100.00
rom_ctrl_csr_aliasing 6.450s 208.636us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.850s 388.294us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.070s 1.029ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.760s 302.654us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 18.140s 1.090ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.930s 1.085ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.420s 212.311us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.330s 207.491us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.330s 207.491us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.010s 800.558us 1 1 100.00
rom_ctrl_csr_rw 6.760s 1.064ms 1 1 100.00
rom_ctrl_csr_aliasing 6.450s 208.636us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.880s 377.034us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.010s 800.558us 1 1 100.00
rom_ctrl_csr_rw 6.760s 1.064ms 1 1 100.00
rom_ctrl_csr_aliasing 6.450s 208.636us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.880s 377.034us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 24.430s 5.093ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.605m 1.061ms 1 1 100.00
rom_ctrl_tl_intg_err 1.090m 1.391ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.605m 1.061ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.605m 1.061ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.605m 1.061ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.605m 1.061ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.570s 345.940us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.570s 345.940us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.570s 345.940us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.090m 1.391ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 13.930s 1.085ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 24.430s 5.093ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.605m 1.061ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 9.650s 578.318us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets