RV_TIMER Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.220m	149.478ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.450s	45.417us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.410s	63.827us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.990s	384.734us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.660s	124.439us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.850s	266.120us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.410s	63.827us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	124.439us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.157m	19.995ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.706m	162.294ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	4.600m	850.759ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	4.600m	850.759ms	1	1	100.00
V2	stress	rv_timer_stress_all	19.455m	722.321ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.370s	32.606us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.460s	196.375us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.460s	196.375us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.450s	45.417us	1	1	100.00
		rv_timer_csr_rw	1.410s	63.827us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	124.439us	1	1	100.00
		rv_timer_same_csr_outstanding	1.600s	17.603us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.450s	45.417us	1	1	100.00
		rv_timer_csr_rw	1.410s	63.827us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	124.439us	1	1	100.00
		rv_timer_same_csr_outstanding	1.600s	17.603us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	2.030s	246.569us	1	1	100.00
		rv_timer_tl_intg_err	1.750s	83.888us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.750s	83.888us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	27.360s	14.983ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			15	16	93.75

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.5327213330356341691070201464878079487013940211163106456815933132870157849703
      Line 272, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14983417760 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 14983417760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---