SPI_DEVICE/1R1W Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.018m	13.116ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.000s	30.303us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.270s	149.000us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.080s	1.044ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.960s	845.936us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.650s	510.156us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.270s	149.000us	1	1	100.00
		spi_device_csr_aliasing	6.960s	845.936us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.660s	66.534us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.370s	174.924us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.620s	22.344us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.440s	6.251us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.920s	5.372us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.170s	191.179us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.170s	191.179us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.360s	389.463us	1	1	100.00
		spi_device_tpm_sts_read	1.640s	182.146us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	20.940s	26.581ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	12.550s	15.029ms	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.530s	305.730us	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.530s	305.730us	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.520s	124.863us	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.520s	124.863us	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.520s	124.863us	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.520s	124.863us	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.520s	124.863us	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.540s	9.876ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	27.000s	45.316ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	27.000s	45.316ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	27.000s	45.316ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.870s	83.513us	1	1	100.00
		spi_device_read_buffer_direct	10.200s	10.604ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	27.000s	45.316ms	1	1	100.00
		spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	17.340s	4.162ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.090s	392.571us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.090s	392.571us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.018m	13.116ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.679m	101.158ms	1	1	100.00
V2	stress_all	spi_device_stress_all	45.940s	6.013ms	1	1	100.00
V2	alert_test	spi_device_alert_test	2.070s	14.267us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.710s	17.214us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.200s	432.271us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.200s	432.271us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.000s	30.303us	1	1	100.00
		spi_device_csr_rw	2.270s	149.000us	1	1	100.00
		spi_device_csr_aliasing	6.960s	845.936us	1	1	100.00
		spi_device_same_csr_outstanding	2.400s	58.811us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.000s	30.303us	1	1	100.00
		spi_device_csr_rw	2.270s	149.000us	1	1	100.00
		spi_device_csr_aliasing	6.960s	845.936us	1	1	100.00
		spi_device_same_csr_outstanding	2.400s	58.811us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.230s	340.388us	1	1	100.00
		spi_device_tl_intg_err	16.230s	3.195ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	16.230s	3.195ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	35.760s	34.036ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.93580333582600558041368122304630748525373824300641733457625134521865645822026
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4691332 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[69])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4691332 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4691332 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[965])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.96414320821664131269625743862630657868301367999589901758018129308593838853361
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4665905 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4665905 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   4673905 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc9168b [110010010001011010001011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   4673905 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xc9168b [110010010001011010001011] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])