SPI_HOST Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	1.367m	13.626ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.320us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	24.010us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	252.203us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	31.066us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	37.702us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	24.010us	1	1	100.00
		spi_host_csr_aliasing	4.000s	31.066us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	41.500us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	23.331us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	5.000s	82.394us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	7.000s	524.532us	1	1	100.00
		spi_host_error_cmd	4.000s	15.631us	1	1	100.00
		spi_host_event	11.000s	660.036us	1	1	100.00
V2	clock_rate	spi_host_speed	6.000s	426.774us	1	1	100.00
V2	speed	spi_host_speed	6.000s	426.774us	1	1	100.00
V2	chip_select_timing	spi_host_speed	6.000s	426.774us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	85.694us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	523.772us	1	1	100.00
V2	cpol_cpha	spi_host_speed	6.000s	426.774us	1	1	100.00
V2	full_cycle	spi_host_speed	6.000s	426.774us	1	1	100.00
V2	duplex	spi_host_smoke	1.367m	13.626ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	1.367m	13.626ms	1	1	100.00
V2	stress_all	spi_host_stress_all	1.050m	21.600ms	1	1	100.00
V2	spien	spi_host_spien	10.000s	693.344us	1	1	100.00
V2	stall	spi_host_status_stall	8.000s	717.086us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	150.377us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	7.000s	524.532us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	45.235us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	28.513us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	78.212us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	78.212us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.320us	1	1	100.00
		spi_host_csr_rw	4.000s	24.010us	1	1	100.00
		spi_host_csr_aliasing	4.000s	31.066us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	58.451us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.320us	1	1	100.00
		spi_host_csr_rw	4.000s	24.010us	1	1	100.00
		spi_host_csr_aliasing	4.000s	31.066us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	58.451us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	57.160us	1	1	100.00
		spi_host_sec_cm	4.000s	118.026us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	57.160us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	40.133m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.68331763997482468401195388740800729988191729231996651706067980781539196602628
      Line 210, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---