SRAM_CTRL/MAIN Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.410s	907.073us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.460s	75.798us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.640s	30.996us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.050s	305.565us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.720s	20.056us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.650s	1.982ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.640s	30.996us	1	1	100.00
		sram_ctrl_csr_aliasing	1.720s	20.056us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.892m	7.141ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	56.010s	9.451ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.538m	16.056ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.699m	21.972ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	22.246m	313.314ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.186m	3.050ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	58.550s	51.804ms	1	1	100.00
V2	executable	sram_ctrl_executable	10.497m	27.694ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	26.330s	1.613ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.746m	16.100ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	13.040s	2.953ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.024m	1.852ms	1	1	100.00
		sram_ctrl_throughput_w_readback	33.950s	851.484us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.830m	20.497ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.030s	345.142us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	16.509m	35.724ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.560s	46.981us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.330s	165.343us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.330s	165.343us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.460s	75.798us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	30.996us	1	1	100.00
		sram_ctrl_csr_aliasing	1.720s	20.056us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	20.465us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.460s	75.798us	1	1	100.00
		sram_ctrl_csr_rw	1.640s	30.996us	1	1	100.00
		sram_ctrl_csr_aliasing	1.720s	20.056us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	20.465us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.290s	7.577ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.470s	2.029us	0	1	0.00
		sram_ctrl_tl_intg_err	2.940s	286.862us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.470s	2.029us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.940s	286.862us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.830m	20.497ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.830m	20.497ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.640s	30.996us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	10.497m	27.694ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	10.497m	27.694ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	10.497m	27.694ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	58.550s	51.804ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.580s	678.927us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.290s	7.577ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.550s	5.062ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.410s	907.073us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.410s	907.073us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	10.497m	27.694ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.470s	2.029us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	58.550s	51.804ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.470s	2.029us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.470s	2.029us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.410s	907.073us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.470s	2.029us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	35.490s	3.006ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.53616597499311215064195806100756486147364906925677010031646816356850595559460
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 678927301 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 678927301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.37966900164629310497040306247348081585512322200824782877276076059723322707644
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2029208 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2029208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---