SRAM_CTRL/RET Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	17.010s	836.491us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.930s	20.929us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.740s	46.163us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.380s	79.179us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.150s	41.209us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.030s	441.828us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.740s	46.163us	1	1	100.00
		sram_ctrl_csr_aliasing	2.150s	41.209us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.500s	294.595us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.330s	1.267ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.294m	11.041ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.825m	2.624ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	33.150s	2.575ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.894m	13.838ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	7.400s	1.622ms	1	1	100.00
V2	executable	sram_ctrl_executable	1.637m	9.100ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	9.170s	3.667ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.192m	72.333ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	41.810s	2.141ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	36.500s	480.163us	1	1	100.00
		sram_ctrl_throughput_w_readback	23.540s	908.048us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.492m	9.787ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.710s	80.894us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	19.805m	44.034ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.510s	13.493us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.260s	129.315us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.260s	129.315us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.930s	20.929us	1	1	100.00
		sram_ctrl_csr_rw	1.740s	46.163us	1	1	100.00
		sram_ctrl_csr_aliasing	2.150s	41.209us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	32.141us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.930s	20.929us	1	1	100.00
		sram_ctrl_csr_rw	1.740s	46.163us	1	1	100.00
		sram_ctrl_csr_aliasing	2.150s	41.209us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.630s	32.141us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.080s	425.256us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.900s	3.138us	0	1	0.00
		sram_ctrl_tl_intg_err	3.820s	726.046us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.900s	3.138us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.820s	726.046us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.492m	9.787ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.492m	9.787ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.740s	46.163us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	1.637m	9.100ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	1.637m	9.100ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	1.637m	9.100ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	7.400s	1.622ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.080s	159.958us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.080s	425.256us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.130s	56.688us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	17.010s	836.491us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	17.010s	836.491us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	1.637m	9.100ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.900s	3.138us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	7.400s	1.622ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.900s	3.138us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.900s	3.138us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	17.010s	836.491us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.900s	3.138us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.718m	1.867ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.65815741258834817523796817966469084848246640871874981043961637835979120907802
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3138478 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3138478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---