UART Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: 0fa5019

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	17.670s	5.685ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.480s	119.355us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.450s	12.298us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.080s	88.735us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.670s	19.202us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.550s	48.278us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.450s	12.298us	1	1	100.00
		uart_csr_aliasing	1.670s	19.202us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	13.640s	38.450ms	1	1	100.00
V2	parity	uart_smoke	17.670s	5.685ms	1	1	100.00
		uart_tx_rx	13.640s	38.450ms	1	1	100.00
V2	parity_error	uart_intr	18.530s	38.979ms	1	1	100.00
		uart_rx_parity_err	1.366m	68.177ms	1	1	100.00
V2	watermark	uart_tx_rx	13.640s	38.450ms	1	1	100.00
		uart_intr	18.530s	38.979ms	1	1	100.00
V2	fifo_full	uart_fifo_full	9.620s	40.082ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	22.840s	84.893ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.443m	47.184ms	1	1	100.00
V2	rx_frame_err	uart_intr	18.530s	38.979ms	1	1	100.00
V2	rx_break_err	uart_intr	18.530s	38.979ms	1	1	100.00
V2	rx_timeout	uart_intr	18.530s	38.979ms	1	1	100.00
V2	perf	uart_perf	1.860m	14.025ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.270s	1.206ms	1	1	100.00
V2	line_loopback	uart_loopback	2.270s	1.206ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	29.890s	59.644ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.410s	2.974ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	13.270s	6.579ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	7.760s	2.128ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	3.676m	64.840ms	1	1	100.00
V2	stress_all	uart_stress_all	4.157m	380.530ms	1	1	100.00
V2	alert_test	uart_alert_test	1.440s	20.278us	1	1	100.00
V2	intr_test	uart_intr_test	1.570s	16.797us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.070s	88.945us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.070s	88.945us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.480s	119.355us	1	1	100.00
		uart_csr_rw	1.450s	12.298us	1	1	100.00
		uart_csr_aliasing	1.670s	19.202us	1	1	100.00
		uart_same_csr_outstanding	1.460s	54.952us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.480s	119.355us	1	1	100.00
		uart_csr_rw	1.450s	12.298us	1	1	100.00
		uart_csr_aliasing	1.670s	19.202us	1	1	100.00
		uart_same_csr_outstanding	1.460s	54.952us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.790s	37.545us	1	1	100.00
		uart_tl_intg_err	1.950s	92.021us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.950s	92.021us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	12.640s	3.673ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00