CHIP Simulation Results

Thursday April 24 2025 17:08:15 UTC

GitHub Revision: `0fa5019`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	34.188s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	34.188s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.201m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.167m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.312m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.875m	5.959ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.875m	5.959ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.875m	5.959ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.333m		0	1	0.00
		chip_sw_example_manufacturer	1.221m		0	1	0.00
		chip_sw_example_concurrency	3.362m	3.728ms	1	1	100.00
		chip_sw_uart_smoketest_signed	18.448s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	16.150s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.340s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.340s		0	1	0.00
V1	xbar_smoke	xbar_smoke	19.970s	63.867us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	11.228s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.193m	6.028ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.934m	5.528ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.163m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	48.229s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.469m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.181m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.700s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.700s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	59.532s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	43.222s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.377m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.377m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.589m	3.129ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.191m	3.666ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.784m	15.034ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.666s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.703s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.023m	15.561ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.553m	6.166ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.485m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.485m	18.018ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.488s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.481s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	10.481s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	12.632s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.451m	5.406ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.240m	4.567ms	1	1	100.00
		chip_sw_aes_idle	4.150m	4.499ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.057m	4.533ms	1	1	100.00
		chip_sw_kmac_idle	3.854m	5.166ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.649s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.279s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.101s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.812s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.219s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.316s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.144s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.140s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.716s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.671s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.956s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.219s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.316s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.144s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.140s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.716s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.671s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.956s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.051s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.910s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.040s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.910s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	53.780s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.961s		0	1	0.00
		chip_sw_clkmgr_jitter	3.309m	3.669ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.072m	5.585ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.604s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	46.430s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.790s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	46.680s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	47.660s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	45.750s	10.340us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.917s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.492s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.514s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.232s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.455m	15.869ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.407m	15.630ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	10.481s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.506s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.407m	15.630ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	15.490s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	21.191s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	22.922s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	12.083s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	19.343s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.455m	15.869ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.784m	15.034ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	21.013m	20.017ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.786m	6.919ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	6.838m	30.022ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.457m	5.475ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.455m	15.869ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.024s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.297s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.455m	15.869ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	13.615s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	6.838m	30.022ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.169s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.848s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.531s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.016s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.040s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.230s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.297s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.700s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	8.506m	9.305ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.894s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.715s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.395s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.305s		0	1	0.00
		chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.232m	9.576ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.713m	11.545ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.393s		0	1	0.00
		chip_prim_tl_access	7.515m	10.109ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.219s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.316s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.144s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.140s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.716s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.671s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.956s		0	1	0.00
		chip_rv_dm_lc_disabled	10.023m	15.561ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.594m	4.702ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	46.910s	10.180us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.496m	5.286ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.150m	4.499ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.235m	3.716ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	48.040s	10.320us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.057m	4.533ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.576m	4.370ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.179m	5.363ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	53.780s	10.360us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.232m	9.576ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.120s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.454m	6.214ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.854m	5.166ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.401s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.401s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.890s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.344m	5.421ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.393s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.232m	9.576ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.910s	10.100us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	16.136s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.051s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.240m	4.567ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.240m	4.567ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.240m	4.567ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.559m	6.429ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.713m	11.545ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.713m	11.545ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.830m	9.551ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.961s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.393s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.455m	15.869ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.377m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.559m	6.429ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.232m	9.576ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.830m	9.551ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.378m	4.431ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.559m	6.429ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.232m	9.576ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.830m	9.551ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.378m	4.431ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.645s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	11.700s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.894s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.715s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.395s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	11.305s		0	1	0.00
		chip_sw_lc_ctrl_transition	16.423s		0	1	0.00
		chip_prim_tl_access	7.515m	10.109ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.515m	10.109ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.560s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.898s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.492s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.051s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.910s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	48.040s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	44.910s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	53.780s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.961s		0	1	0.00
		chip_sw_clkmgr_jitter	3.309m	3.669ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.186m	7.859ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.186m	7.859ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.192m	3.944ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.407m	4.924ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.933m	4.392ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.538m	6.161ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.278m	3.809ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.442m	4.895ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.378m	4.431ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	21.013m	20.017ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	21.013m	20.017ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.967m	4.369ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.872m	5.683ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.837m	3.700ms	1	1	100.00
		chip_sw_csrng_smoketest	3.275m	4.394ms	1	1	100.00
		chip_sw_gpio_smoketest	3.502m	5.236ms	1	1	100.00
		chip_sw_hmac_smoketest	4.163m	4.417ms	1	1	100.00
		chip_sw_kmac_smoketest	3.502m	3.405ms	1	1	100.00
		chip_sw_otbn_smoketest	5.232m	5.713ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.146m	4.549ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.514m	4.023ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.282m	5.817ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.227m	3.289ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.564m	3.755ms	1	1	100.00
		chip_sw_uart_smoketest	3.890m	4.611ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	17.789s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	18.448s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	11.228s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	10.332s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.680m	4.878ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.086m	5.835ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.065m	3.926ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.328m	4.882ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.464s		0	1	0.00
		chip_rv_dm_lc_disabled	10.023m	15.561ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.245s		0	1	0.00
		chip_sw_lc_walkthrough_prod	13.390s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	15.750s		0	1	0.00
		chip_sw_lc_walkthrough_rma	14.214s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.464s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.932s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.463s		0	1	0.00
		rom_volatile_raw_unlock	12.053s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.446s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.480m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.223m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.960m	5.385ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.960m	5.385ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.340s		0	1	0.00
		chip_same_csr_outstanding	12.670s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.340s		0	1	0.00
		chip_same_csr_outstanding	12.670s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.139m	62.309us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.250s	12.652us	1	1	100.00
		xbar_smoke_large_delays	4.595m	2.443ms	1	1	100.00
		xbar_smoke_slow_rsp	5.145m	1.887ms	1	1	100.00
		xbar_random_zero_delays	15.910s	16.856us	1	1	100.00
		xbar_random_large_delays	11.534m	5.887ms	1	1	100.00
		xbar_random_slow_rsp	20.541m	7.503ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.800m	222.384us	1	1	100.00
		xbar_error_and_unmapped_addr	6.790s	7.499us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.908m	334.690us	1	1	100.00
		xbar_error_and_unmapped_addr	6.790s	7.499us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.648m	425.193us	1	1	100.00
		xbar_access_same_device_slow_rsp	47.016m	18.916ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	8.640s	9.726us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.701m	93.412us	1	1	100.00
		xbar_stress_all_with_error	12.405m	2.270ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	16.460m	1.390ms	1	1	100.00
		xbar_stress_all_with_reset_error	19.645m	905.052us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.376s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.375s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.730s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.450s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.325s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.686s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.476s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.659s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.624s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	13.237s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.645s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	13.593s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.940s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.193s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.006s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.151s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.413s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.924s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.941s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.439s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	13.732s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.868s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.279s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.338s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.268s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.787s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.023s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.077s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.867s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.539s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.025s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	13.671s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.796s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.788s		0	1	0.00
		rom_e2e_asm_init_dev	13.363s		0	1	0.00
		rom_e2e_asm_init_prod	11.936s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.451s		0	1	0.00
		rom_e2e_asm_init_rma	10.811s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.894s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.995s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.865s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.328s		0	1	0.00
V2		TOTAL			66	205	32.20
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.522m	3.729ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.306m	4.762ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.906s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.286s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.722s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.374s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.455m	15.869ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	14.160s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.628m	14.739ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.045s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.368s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.906s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.286s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.722s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.970s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.358s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.542s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	41.157s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.253m	12.818ms	1	1	100.00
		chip_plic_all_irqs_0	8.559m	5.197ms	1	1	100.00
		chip_plic_all_irqs_10	10.043m	6.504ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.533m	4.151ms	1	1	100.00
		chip_sw_dma_abort	4.288m	4.212ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.899s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.435s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.541s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.713s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.454s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.404s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.717s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.191s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.627s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.862s		0	1	0.00
		chip_sw_mbx_smoketest	4.159m	4.052ms	1	1	100.00
		TOTAL			77	247	31.17

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.69001127568214607846601091574810352984337523664148874870572226871986301394424
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Target //sw/device/tests:example_test_from_rom_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (d5a2a0)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (a53019)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 67.039s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.103311833118528024846392615063644130006779665216242088698416271363108445710316
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (11542a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 61.691s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.81912082035799718595366883382841662051702405014917086474257394963239457542990
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (d5f8e2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 132.218s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.14667453051041842916169494680611871937990015104677990240068120923005174594592
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (a6f1f8)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 49.122s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.93434028621213310657620818883461840827223520540477017110085788916090001440080
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (aedcf8)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 33.104s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.60901334668659434781103265566396775574258123546041697406520634353352521344547
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.25790336098681046261333721638285527755063702914038678625860548517668082197147
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.42304295893108394119332065603935476849591740863215386050018900484115217355773
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.55006569096035008246459144586185313496270175455934738794295190754040941082417
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.89821041252776912114199360105704059306220431718906270166138741679034244545401
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.99342832393546592076808292123867639758061267789032741441701622081125950554656
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.5699437259494469148543403902791550940238500867568234437852302114885206899708
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.6079457439008191814219720278603506738550225941122482926564674128619953121552
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.85330279642983215927453555703470320201373950357045889407535497882147268721248
Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30021.543730 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30021.543730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.72536711178764868588253757351415186420157873397450603338005880983936994127670
Line 481, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20017.394803 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20017.394803 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.45888203018673034537664700938917715555213490695857385129022665356130307127169
Line 415, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.638387 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.638387 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.65258529570607297358024696903832153090689765511039042139159793854712043870496
Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9576.286688 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (23475574564594006549067431457453114342829507683132634116926655184845193282304 [0x33e6b44fa8bcec3dcde0a9af5c60067954a744a64609ab755fd04924ae2f0300] vs 49276844403494215345889251065917546303745199615904835793117813493348961763750 [0x6cf1b49f7aa4d804e30b1d4881e4d3a8d6450a1bdcc7ea6a4bb529ab4d5641a6])
  UVM_INFO @ 9576.286688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.89396847000345835915951220740537694200842659217609709497878866994633034960701
Line 488, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 9304.816210 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (1723343727245031967959274880721432794111142361349189854394702856539220594137 [0x3cf60c387490fd2630e54c7b2ddfa3e1fddc1323e513ada4141ad291af5cdd9] vs 101773166427830890825252488155251195072236198326916319239186651861658979539836 [0xe1019224e3f47afc580b89ccce732ec0b035d6eea3bf06482886f5cf57341b7c])
  UVM_INFO @ 9304.816210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.41444469420436702735921259441958944907343477093940544996245832166100627700407
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3128.658118 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h73d68636  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h0  a_user: 'h26906  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3128.658118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.91194110813191857712912601060817999152410815080041438054014316943914674237745
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3665.514876 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hf79ea1e5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h0  a_user: 'h26915  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3665.514876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.4724345410559633471852734220848341539342783639145580924340634869715014661418
    Line 479, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5527.532000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5527.532000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.61141182696726536525630710521252342194989911805584977518549231452139823094483
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3944.257148 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3944.257148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.82346018017093957525350915686796233978310267820891468275263141606527717777214
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6160.805352 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6160.805352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.16169217307426385331187717138208858006687041741904659596945360006640001671151
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36788) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.60969336492070998718845908371812599864811156293453091952294596400415501945558
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5384.874040 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36788) { a_addr: 'h2210  a_data: 'h1a43f8cc  a_mask: 'h0  a_size: 'h2  a_param: 'h0  a_source: 'hf6  a_opcode: 'h4  a_user: 'h26347  d_param: 'h0  d_source: 'hf6  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5384.874040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.82378330521545957325467706529935488901624889799706408860795474640846439174854
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15034.294468 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15034.294468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.63566874987452712201896317031766050654110044766582316263030976570907866791135
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.31255058348004125503955775100800518468557223322944629542691021511980483114357
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4212.068196 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4212.068196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```