DMA Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	9.000s	1.289ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	284.813us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	716.921us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	20.209us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	15.069us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	8.000s	305.210us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	322.687us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	126.574us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	15.069us	1	1	100.00
		dma_csr_aliasing	8.000s	322.687us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.000m	12.651ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	30.750m	3.192s	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	29.767m	165.257ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	1.667m	7.328ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	30.750m	3.192s	1	1	100.00
V2	dma_abort	dma_abort	16.000s	3.822ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.667m	9.087ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	17.507us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	542.986us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	542.986us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	20.209us	1	1	100.00
		dma_csr_rw	4.000s	15.069us	1	1	100.00
		dma_csr_aliasing	8.000s	322.687us	1	1	100.00
		dma_same_csr_outstanding	5.000s	49.548us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	20.209us	1	1	100.00
		dma_csr_rw	4.000s	15.069us	1	1	100.00
		dma_csr_aliasing	8.000s	322.687us	1	1	100.00
		dma_same_csr_outstanding	5.000s	49.548us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	25.000s	1.060ms	1	1	100.00
		dma_generic_stress	1.667m	7.328ms	1	1	100.00
		dma_handshake_stress	30.750m	3.192s	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	555.869us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	2.300m	8.271ms	1	1	100.00
		dma_longer_transfer	6.000s	302.491us	1	1	100.00
		TOTAL			21	21	100.00