EDN Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.830s 54.071us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.920s 17.942us 1 1 100.00
V1 csr_rw edn_csr_rw 1.860s 84.387us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.470s 69.452us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.980s 50.463us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.920s 39.281us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.860s 84.387us 1 1 100.00
edn_csr_aliasing 1.980s 50.463us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.770s 71.801us 1 1 100.00
V2 csrng_commands edn_genbits 2.770s 71.801us 1 1 100.00
V2 genbits edn_genbits 2.770s 71.801us 1 1 100.00
V2 interrupts edn_intr 1.630s 36.056us 1 1 100.00
V2 alerts edn_alert 2.010s 99.681us 1 1 100.00
V2 errs edn_err 2.110s 210.926us 1 1 100.00
V2 disable edn_disable 1.670s 32.730us 1 1 100.00
edn_disable_auto_req_mode 1.780s 87.986us 1 1 100.00
V2 stress_all edn_stress_all 4.620s 241.094us 1 1 100.00
V2 intr_test edn_intr_test 1.710s 25.423us 1 1 100.00
V2 alert_test edn_alert_test 1.840s 36.942us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.120s 42.729us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.120s 42.729us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.920s 17.942us 1 1 100.00
edn_csr_rw 1.860s 84.387us 1 1 100.00
edn_csr_aliasing 1.980s 50.463us 1 1 100.00
edn_same_csr_outstanding 1.930s 126.166us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.920s 17.942us 1 1 100.00
edn_csr_rw 1.860s 84.387us 1 1 100.00
edn_csr_aliasing 1.980s 50.463us 1 1 100.00
edn_same_csr_outstanding 1.930s 126.166us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 5.020s 275.260us 1 1 100.00
edn_tl_intg_err 2.860s 476.129us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.960s 18.330us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.010s 99.681us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.020s 275.260us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.020s 275.260us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 5.020s 275.260us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.020s 275.260us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.010s 99.681us 1 1 100.00
edn_sec_cm 5.020s 275.260us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.010s 99.681us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.860s 476.129us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets