HMAC Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.160s 653.945us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.810s 15.235us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.740s 16.444us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 9.130s 704.820us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.400s 330.110us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.160s 36.529us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.740s 16.444us 1 1 100.00
hmac_csr_aliasing 3.400s 330.110us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 22.960s 460.382us 1 1 100.00
V2 back_pressure hmac_back_pressure 51.010s 7.023ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.560s 176.153us 1 1 100.00
hmac_test_sha384_vectors 21.980s 389.630us 1 1 100.00
hmac_test_sha512_vectors 6.354m 45.955ms 1 1 100.00
hmac_test_hmac256_vectors 9.440s 276.931us 1 1 100.00
hmac_test_hmac384_vectors 9.460s 257.362us 1 1 100.00
hmac_test_hmac512_vectors 11.890s 644.093us 1 1 100.00
V2 burst_wr hmac_burst_wr 35.110s 2.395ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 9.458m 28.207ms 1 1 100.00
V2 error hmac_error 36.110s 7.690ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 46.720s 1.268ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.160s 653.945us 1 1 100.00
hmac_long_msg 22.960s 460.382us 1 1 100.00
hmac_back_pressure 51.010s 7.023ms 1 1 100.00
hmac_datapath_stress 9.458m 28.207ms 1 1 100.00
hmac_burst_wr 35.110s 2.395ms 1 1 100.00
hmac_stress_all 2.272m 11.160ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.160s 653.945us 1 1 100.00
hmac_long_msg 22.960s 460.382us 1 1 100.00
hmac_back_pressure 51.010s 7.023ms 1 1 100.00
hmac_datapath_stress 9.458m 28.207ms 1 1 100.00
hmac_wipe_secret 46.720s 1.268ms 1 1 100.00
hmac_test_sha256_vectors 9.560s 176.153us 1 1 100.00
hmac_test_sha384_vectors 21.980s 389.630us 1 1 100.00
hmac_test_sha512_vectors 6.354m 45.955ms 1 1 100.00
hmac_test_hmac256_vectors 9.440s 276.931us 1 1 100.00
hmac_test_hmac384_vectors 9.460s 257.362us 1 1 100.00
hmac_test_hmac512_vectors 11.890s 644.093us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.160s 653.945us 1 1 100.00
hmac_long_msg 22.960s 460.382us 1 1 100.00
hmac_back_pressure 51.010s 7.023ms 1 1 100.00
hmac_datapath_stress 9.458m 28.207ms 1 1 100.00
hmac_burst_wr 35.110s 2.395ms 1 1 100.00
hmac_error 36.110s 7.690ms 1 1 100.00
hmac_wipe_secret 46.720s 1.268ms 1 1 100.00
hmac_test_sha256_vectors 9.560s 176.153us 1 1 100.00
hmac_test_sha384_vectors 21.980s 389.630us 1 1 100.00
hmac_test_sha512_vectors 6.354m 45.955ms 1 1 100.00
hmac_test_hmac256_vectors 9.440s 276.931us 1 1 100.00
hmac_test_hmac384_vectors 9.460s 257.362us 1 1 100.00
hmac_test_hmac512_vectors 11.890s 644.093us 1 1 100.00
hmac_stress_all 2.272m 11.160ms 1 1 100.00
V2 stress_all hmac_stress_all 2.272m 11.160ms 1 1 100.00
V2 alert_test hmac_alert_test 1.530s 34.782us 1 1 100.00
V2 intr_test hmac_intr_test 1.480s 39.067us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.490s 65.010us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.490s 65.010us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.810s 15.235us 1 1 100.00
hmac_csr_rw 1.740s 16.444us 1 1 100.00
hmac_csr_aliasing 3.400s 330.110us 1 1 100.00
hmac_same_csr_outstanding 2.820s 1.591ms 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.810s 15.235us 1 1 100.00
hmac_csr_rw 1.740s 16.444us 1 1 100.00
hmac_csr_aliasing 3.400s 330.110us 1 1 100.00
hmac_same_csr_outstanding 2.820s 1.591ms 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.820s 157.126us 1 1 100.00
hmac_tl_intg_err 4.520s 270.602us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.520s 270.602us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.160s 653.945us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.940s 657.531us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 36.000s 4.900ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 5.470s 254.263us 1 1 100.00
TOTAL 28 28 100.00