I2C Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.121m	1.960ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	28.690s	1.284ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.730s	58.469us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.660s	25.161us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.960s	2.250ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.180s	119.898us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.910s	40.170us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.660s	25.161us	1	1	100.00
		i2c_csr_aliasing	2.180s	119.898us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	7.630s	961.743us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.327m	58.471ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	9.950s	2.216ms	1	1	100.00
V2	host_override	i2c_host_override	1.810s	90.282us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	50.910s	14.183ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	33.820s	2.179ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.930s	232.791us	1	1	100.00
		i2c_host_fifo_fmt_empty	9.180s	1.340ms	1	1	100.00
		i2c_host_fifo_reset_rx	8.210s	203.381us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	51.740s	5.396ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.560s	534.043us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.990s	114.180us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.810s	15.935ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	38.230s	84.543ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.980s	3.183ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.260s	5.140ms	1	1	100.00
		i2c_target_intr_smoke	5.060s	3.327ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.350s	268.000us	1	1	100.00
		i2c_target_fifo_reset_tx	1.880s	302.824us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	16.133m	67.324ms	1	1	100.00
		i2c_target_stress_rd	16.260s	5.140ms	1	1	100.00
		i2c_target_intr_stress_wr	39.250s	23.828ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	7.590s	6.348ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	6.680s	2.739ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	7.400s	1.473ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.550s	198.996us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.710s	570.160us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.100s	180.737us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	9.950s	2.216ms	1	1	100.00
		i2c_host_perf_precise	4.360s	220.550us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.560s	534.043us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.420s	103.368us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.210s	2.348ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.720s	530.073us	1	1	100.00
		i2c_target_nack_txstretch	2.440s	568.464us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	7.060s	1.164ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.440s	4.656ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.430s	23.555us	1	1	100.00
V2	intr_test	i2c_intr_test	1.610s	17.077us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.810s	37.294us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.810s	37.294us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.730s	58.469us	1	1	100.00
		i2c_csr_rw	1.660s	25.161us	1	1	100.00
		i2c_csr_aliasing	2.180s	119.898us	1	1	100.00
		i2c_same_csr_outstanding	1.850s	207.983us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.730s	58.469us	1	1	100.00
		i2c_csr_rw	1.660s	25.161us	1	1	100.00
		i2c_csr_aliasing	2.180s	119.898us	1	1	100.00
		i2c_same_csr_outstanding	1.850s	207.983us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.780s	124.425us	1	1	100.00
		i2c_sec_cm	1.770s	239.816us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.780s	124.425us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	9.550s	1.319ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.350s	57.668us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	20.490s	753.771us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.1733388682465822276929957799284460521906700844724655311648064246694669031355
      Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1318850447 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1318850447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.40461404930560779211012591608039757060660471342365397398136916821209783581204
      Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 753771154 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 753771154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.87795997233128593436271520496491480702821909055570235328555642204501222433755
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  57668455 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 191 [0xbf])
        UVM_INFO @  57668455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.26916694105659284382268939899213314432114576379433318705866571213822552895401
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 114180165 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------