KEYMGR Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	9.900s	8.164ms	1	1	100.00
V1	random	keymgr_random	5.160s	1.069ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.010s	47.230us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.080s	45.341us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	6.050s	2.210ms	0	1	0.00
V1	csr_aliasing	keymgr_csr_aliasing	5.580s	450.915us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.790s	109.901us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.080s	45.341us	1	1	100.00
		keymgr_csr_aliasing	5.580s	450.915us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.860s	346.680us	1	1	100.00
V2	sideload	keymgr_sideload	3.020s	64.482us	1	1	100.00
		keymgr_sideload_kmac	2.650s	129.701us	1	1	100.00
		keymgr_sideload_aes	3.310s	437.936us	1	1	100.00
		keymgr_sideload_otbn	3.390s	366.399us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	4.380s	138.997us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.240s	272.047us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.150s	577.230us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	5.460s	610.608us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.600s	80.986us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.690s	236.015us	1	1	100.00
V2	stress_all	keymgr_stress_all	25.750s	1.314ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.710s	111.429us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.610s	64.275us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.180s	41.417us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.180s	41.417us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.010s	47.230us	1	1	100.00
		keymgr_csr_rw	2.080s	45.341us	1	1	100.00
		keymgr_csr_aliasing	5.580s	450.915us	1	1	100.00
		keymgr_same_csr_outstanding	2.410s	53.326us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.010s	47.230us	1	1	100.00
		keymgr_csr_rw	2.080s	45.341us	1	1	100.00
		keymgr_csr_aliasing	5.580s	450.915us	1	1	100.00
		keymgr_same_csr_outstanding	2.410s	53.326us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
		keymgr_tl_intg_err	2.820s	136.615us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.920s	1.587ms	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.920s	1.587ms	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.920s	1.587ms	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.920s	1.587ms	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.690s	12.183us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.820s	136.615us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.920s	1.587ms	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.860s	346.680us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	5.160s	1.069ms	1	1	100.00
		keymgr_csr_rw	2.080s	45.341us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	5.160s	1.069ms	1	1	100.00
		keymgr_csr_rw	2.080s	45.341us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	5.160s	1.069ms	1	1	100.00
		keymgr_csr_rw	2.080s	45.341us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.240s	272.047us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.600s	80.986us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.600s	80.986us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	5.160s	1.069ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.840s	333.090us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.370s	257.679us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.240s	272.047us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.370s	257.679us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.370s	257.679us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.370s	257.679us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.980s	1.138ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.370s	257.679us	1	1	100.00
V2S		TOTAL			4	6	66.67
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	6.410s	181.982us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 3 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.32681202236513595548963173846032351925041428676858077173485790182372379616017
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
        UVM_ERROR @  12182851 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_1_rd_A
        UVM_INFO @  12182851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.19165618126648139447237990514864842035764624821816770195679735774432089052118
      Line 135, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
        UVM_ERROR @ 136614689 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
        UVM_INFO @ 136614689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_bit_bash has 1 failures.

    • 0.keymgr_csr_bit_bash.94980824786391149475617154714002619412842482574231360660154911413665349614656
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
        UVM_ERROR @ 2209810570 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
        UVM_INFO @ 2209810570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---