KMAC/MASKED Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	13.000s	1.662ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.930s	56.819us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.850s	94.343us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.730s	1.477ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.480s	1.805ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.980s	74.296us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.850s	94.343us	1	1	100.00
		kmac_csr_aliasing	7.480s	1.805ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.830s	25.513us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.960s	75.841us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	21.488m	185.571ms	1	1	100.00
V2	burst_write	kmac_burst_write	20.228m	30.254ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.660s	7.203ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.259m	349.556ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.760s	1.629ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.959m	32.646ms	1	1	100.00
		kmac_test_vectors_shake_128	3.186m	29.440ms	1	1	100.00
		kmac_test_vectors_shake_256	28.574m	243.456ms	1	1	100.00
		kmac_test_vectors_kmac	3.210s	239.008us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.140s	300.183us	1	1	100.00
V2	sideload	kmac_sideload	30.220s	2.613ms	1	1	100.00
V2	app	kmac_app	4.614m	61.381ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.691m	37.094ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.890m	17.513ms	1	1	100.00
V2	error	kmac_error	10.610s	2.159ms	1	1	100.00
V2	key_error	kmac_key_error	7.350s	4.459ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.150s	40.874us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	2.060s	22.018us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.860s	31.593us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.001m	10.890ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.320s	68.091us	1	1	100.00
V2	stress_all	kmac_stress_all	36.927m	118.106ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.760s	38.509us	1	1	100.00
V2	alert_test	kmac_alert_test	1.690s	19.805us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.880s	90.239us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.880s	90.239us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.930s	56.819us	1	1	100.00
		kmac_csr_rw	1.850s	94.343us	1	1	100.00
		kmac_csr_aliasing	7.480s	1.805ms	1	1	100.00
		kmac_same_csr_outstanding	2.740s	113.367us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.930s	56.819us	1	1	100.00
		kmac_csr_rw	1.850s	94.343us	1	1	100.00
		kmac_csr_aliasing	7.480s	1.805ms	1	1	100.00
		kmac_same_csr_outstanding	2.740s	113.367us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.440s	265.485us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.440s	265.485us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.440s	265.485us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.440s	265.485us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.470s	93.042us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	34.460s	9.359ms	1	1	100.00
		kmac_tl_intg_err	4.220s	893.349us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.220s	893.349us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.320s	68.091us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	13.000s	1.662ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	30.220s	2.613ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.440s	265.485us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	34.460s	9.359ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	34.460s	9.359ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	34.460s	9.359ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	13.000s	1.662ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.320s	68.091us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	34.460s	9.359ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.000m	1.575ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	13.000s	1.662ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	7.910s	1.197ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.60727427924101745363663853436920587220337819166675147618156852521181970317011
      Line 95, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1197242722 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 1197242722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---