KMAC/UNMASKED Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	5.350s	1.068ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.890s	254.538us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.780s	56.370us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.880s	287.426us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.900s	634.719us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.060s	295.964us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.780s	56.370us	1	1	100.00
		kmac_csr_aliasing	7.900s	634.719us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.620s	10.847us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.300s	128.000us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	6.270m	84.240ms	1	1	100.00
V2	burst_write	kmac_burst_write	32.640s	1.583ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.880s	14.967ms	1	1	100.00
		kmac_test_vectors_sha3_256	31.250s	9.508ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.290m	57.087ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.340s	2.870ms	1	1	100.00
		kmac_test_vectors_shake_128	2.410m	32.893ms	1	1	100.00
		kmac_test_vectors_shake_256	1.501m	24.045ms	1	1	100.00
		kmac_test_vectors_kmac	2.670s	173.355us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.630s	1.043ms	1	1	100.00
V2	sideload	kmac_sideload	45.810s	3.760ms	1	1	100.00
V2	app	kmac_app	1.012m	34.580ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.910s	104.496us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	34.930s	2.018ms	1	1	100.00
V2	error	kmac_error	3.746m	57.148ms	1	1	100.00
V2	key_error	kmac_key_error	7.460s	1.500ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.280s	308.469us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	8.720s	2.494ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	9.800s	647.156us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	10.510s	1.339ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.950s	258.545us	1	1	100.00
V2	stress_all	kmac_stress_all	28.270s	1.299ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.500s	38.159us	1	1	100.00
V2	alert_test	kmac_alert_test	1.640s	52.817us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.390s	51.938us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.390s	51.938us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.890s	254.538us	1	1	100.00
		kmac_csr_rw	1.780s	56.370us	1	1	100.00
		kmac_csr_aliasing	7.900s	634.719us	1	1	100.00
		kmac_same_csr_outstanding	2.200s	76.742us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.890s	254.538us	1	1	100.00
		kmac_csr_rw	1.780s	56.370us	1	1	100.00
		kmac_csr_aliasing	7.900s	634.719us	1	1	100.00
		kmac_same_csr_outstanding	2.200s	76.742us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.270s	80.329us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.270s	80.329us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.270s	80.329us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.270s	80.329us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.070s	113.853us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	20.000s	1.804ms	1	1	100.00
		kmac_tl_intg_err	4.050s	140.840us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.050s	140.840us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.950s	258.545us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	5.350s	1.068ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	45.810s	3.760ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.270s	80.329us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	20.000s	1.804ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	20.000s	1.804ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	20.000s	1.804ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	5.350s	1.068ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.950s	258.545us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	20.000s	1.804ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.240m	21.435ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	5.350s	1.068ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	50.260s	12.922ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.53394205045785693001747595671795099143662671267846773699725708776105400883238
      Line 109, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12921915879 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12921915879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---