841f73f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 1.283m | 20.453ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 25.684us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 3.000s | 43.107us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 20.765us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 3.000s | 14.625us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.124us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 3.000s | 43.107us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 3.000s | 14.625us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 1.183m | 2.033ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 45.000s | 4.190ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 47.000s | 27.238ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 16.424us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 1.173us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 1.173us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 25.684us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 43.107us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 14.625us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 35.786us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 25.684us | 1 | 1 | 100.00 |
| mbx_csr_rw | 3.000s | 43.107us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 3.000s | 14.625us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 35.786us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 27.234us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 7.015us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.15329937417021488601344341102365683050530375365726302492585242809086335982129
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1172627 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xac78789b a_data = 0xf180105c a_mask = 0x8 a_size = 0x1 a_param = 0x0 a_source = 0xf8 a_opcode = PutPartialData a_user = 0x24da7 d_data = 0x97c3b9fc d_size = 0x1 d_param = 0x0 d_source = 0x9c d_opcode = AccessAckData d_error = 0 d_user = 11011010001000 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1172627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.67100064615801988344849366714457049537964652229823797372608857321749436437414
Line 96, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 7015308 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x291aa8f4 a_data = 0x5c0c18e4 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x6b a_opcode = Get a_user = 0x25afa d_data = 0xdbad30e0 d_size = 0x0 d_param = 0x0 d_source = 0xaa d_opcode = AccessAckData d_error = 0 d_user = 10101100100101 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 7015308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.80547707383963829516751278364231088254070968275246855121879178173178517137135
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1123785 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x3017e4b0 a_data = 0x3a1e77e0 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x82 a_opcode = Get a_user = 0x344b9 d_data = 0x31de3e0a d_size = 0x3 d_param = 0x0 d_source = 0xef d_opcode = AccessAck d_error = 0 d_user = 10011001010011 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1123785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---