OTBN Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	137.924us	1	1	100.00
V1	single_binary	otbn_single	7.000s	13.243us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	8.000s	22.846us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	61.591us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	90.816us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	18.585us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	20.495us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	61.591us	1	1	100.00
		otbn_csr_aliasing	6.000s	18.585us	1	1	100.00
V1	mem_walk	otbn_mem_walk	17.000s	634.303us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	15.000s	405.762us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	20.000s	79.426us	1	1	100.00
V2	multi_error	otbn_multi_err	49.000s	293.431us	1	1	100.00
V2	back_to_back	otbn_multi	37.000s	115.768us	1	1	100.00
V2	stress_all	otbn_stress_all	33.000s	237.553us	1	1	100.00
V2	lc_escalation	otbn_escalate	7.000s	35.560us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	26.635us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	8.000s	15.457us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	21.268us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	12.696us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	25.028us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	25.028us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	8.000s	22.846us	1	1	100.00
		otbn_csr_rw	6.000s	61.591us	1	1	100.00
		otbn_csr_aliasing	6.000s	18.585us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	16.467us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	8.000s	22.846us	1	1	100.00
		otbn_csr_rw	6.000s	61.591us	1	1	100.00
		otbn_csr_aliasing	6.000s	18.585us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	16.467us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	263.683us	1	1	100.00
		otbn_dmem_err	9.000s	13.736us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	58.023us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	129.390us	1	1	100.00
		otbn_mac_bignum_acc_err	11.000s	237.674us	1	1	100.00
		otbn_urnd_err	7.000s	9.608us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	22.561us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	32.498us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	9.000s	34.028us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
		otbn_tl_intg_err	19.000s	228.680us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	27.000s	366.824us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	137.924us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	9.000s	13.736us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	263.683us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	19.000s	228.680us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	7.000s	35.560us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	263.683us	1	1	100.00
		otbn_dmem_err	9.000s	13.736us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	26.635us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	22.561us	1	1	100.00
		otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	7.000s	13.243us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	263.683us	1	1	100.00
		otbn_dmem_err	9.000s	13.736us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	26.635us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	22.561us	1	1	100.00
		otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	7.000s	35.560us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	263.683us	1	1	100.00
		otbn_dmem_err	9.000s	13.736us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	26.635us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	22.561us	1	1	100.00
		otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	7.000s	13.243us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	8.000s	62.375us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	7.000s	24.221us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	18.000s	783.069us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	18.000s	783.069us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	12.000s	82.845us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	118.973us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	63.777us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	63.777us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	38.553us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	7.000s	13.243us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	7.000s	13.243us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	7.000s	13.243us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	37.000s	115.768us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	7.000s	13.243us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	7.000s	13.243us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	12.000s	28.563us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	7.000s	13.243us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	3.217m	2.196ms	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.450m	513.145us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.60949603099928971289846716833359227507133388028313896388643633103146107014143
      Line 256, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 513144693 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 513144693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.40426555484800298730592903898166839192615842194930471967904033524881573143009
      Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 38552771 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  38552771 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  38552771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---