RV_TIMER Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.580s	14.737us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.550s	47.570us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.400s	40.729us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.340s	251.093us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.630s	222.365us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.050s	86.200us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.400s	40.729us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	222.365us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.680s	110.475us	1	1	100.00
V2	disabled	rv_timer_disabled	10.500s	18.442ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	14.240s	29.646ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	14.240s	29.646ms	1	1	100.00
V2	stress	rv_timer_stress_all	1.550s	50.064us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.540s	12.964us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.490s	32.941us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.490s	32.941us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.550s	47.570us	1	1	100.00
		rv_timer_csr_rw	1.400s	40.729us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	222.365us	1	1	100.00
		rv_timer_same_csr_outstanding	1.650s	36.085us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.550s	47.570us	1	1	100.00
		rv_timer_csr_rw	1.400s	40.729us	1	1	100.00
		rv_timer_csr_aliasing	1.630s	222.365us	1	1	100.00
		rv_timer_same_csr_outstanding	1.650s	36.085us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.980s	100.837us	1	1	100.00
		rv_timer_tl_intg_err	1.990s	182.060us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.990s	182.060us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	45.510s	5.799ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00