SPI_DEVICE/1R1W Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	27.080s	1.840ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.920s	240.437us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.770s	184.322us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.510s	1.863ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.440s	325.692us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.760s	150.859us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.770s	184.322us	1	1	100.00
		spi_device_csr_aliasing	15.440s	325.692us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.440s	13.947us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.020s	41.012us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.630s	58.168us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.540s	7.887us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.600s	4.037us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.740s	76.707us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.740s	76.707us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	6.550s	20.338ms	1	1	100.00
		spi_device_tpm_sts_read	1.600s	138.940us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.860s	4.128ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	13.130s	50.228ms	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.150s	9.642ms	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.150s	9.642ms	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.660s	158.018us	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.660s	158.018us	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.660s	158.018us	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.660s	158.018us	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.660s	158.018us	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.750s	1.568ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	19.400s	1.829ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	19.400s	1.829ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	19.400s	1.829ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.460s	1.227ms	1	1	100.00
		spi_device_read_buffer_direct	9.830s	1.351ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	19.400s	1.829ms	1	1	100.00
		spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.321m	68.597ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.550s	517.657us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.550s	517.657us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	27.080s	1.840ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.466m	131.659ms	1	1	100.00
V2	stress_all	spi_device_stress_all	7.320m	290.956ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.380s	13.797us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.550s	17.176us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.180s	117.814us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.180s	117.814us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.920s	240.437us	1	1	100.00
		spi_device_csr_rw	2.770s	184.322us	1	1	100.00
		spi_device_csr_aliasing	15.440s	325.692us	1	1	100.00
		spi_device_same_csr_outstanding	3.210s	120.642us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.920s	240.437us	1	1	100.00
		spi_device_csr_rw	2.770s	184.322us	1	1	100.00
		spi_device_csr_aliasing	15.440s	325.692us	1	1	100.00
		spi_device_same_csr_outstanding	3.210s	120.642us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.780s	93.490us	1	1	100.00
		spi_device_tl_intg_err	6.320s	306.494us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.320s	306.494us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	11.100s	1.831ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.97734450768670777115704043002576083048668938881259746852404040804930306090548
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4973865 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[27])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4973865 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4973865 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[923])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.81210455699596716906955713506980114552524750641893802060486949579081591689632
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3422043 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   3422043 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   3497043 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x97725 [10010111011100100101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   3497043 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x97725 [10010111011100100101] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])