SPI_HOST Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	44.000s	6.140ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	47.167us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	28.518us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	166.336us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	23.349us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	30.863us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	28.518us	1	1	100.00
		spi_host_csr_aliasing	4.000s	23.349us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	46.499us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	23.087us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	173.371us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	18.000s	1.158ms	1	1	100.00
		spi_host_error_cmd	4.000s	42.419us	1	1	100.00
		spi_host_event	13.000s	1.329ms	1	1	100.00
V2	clock_rate	spi_host_speed	17.000s	3.290ms	1	1	100.00
V2	speed	spi_host_speed	17.000s	3.290ms	1	1	100.00
V2	chip_select_timing	spi_host_speed	17.000s	3.290ms	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	109.435us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	1.505ms	1	1	100.00
V2	cpol_cpha	spi_host_speed	17.000s	3.290ms	1	1	100.00
V2	full_cycle	spi_host_speed	17.000s	3.290ms	1	1	100.00
V2	duplex	spi_host_smoke	44.000s	6.140ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	44.000s	6.140ms	1	1	100.00
V2	stress_all	spi_host_stress_all	14.000s	619.620us	1	1	100.00
V2	spien	spi_host_spien	20.000s	1.926ms	1	1	100.00
V2	stall	spi_host_status_stall	11.000s	747.705us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	57.561us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	18.000s	1.158ms	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	27.469us	1	1	100.00
V2	intr_test	spi_host_intr_test	3.000s	23.767us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	99.171us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	99.171us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	47.167us	1	1	100.00
		spi_host_csr_rw	4.000s	28.518us	1	1	100.00
		spi_host_csr_aliasing	4.000s	23.349us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	53.776us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	47.167us	1	1	100.00
		spi_host_csr_rw	4.000s	28.518us	1	1	100.00
		spi_host_csr_aliasing	4.000s	23.349us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	53.776us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	177.430us	1	1	100.00
		spi_host_sec_cm	4.000s	235.741us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	177.430us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	29.767m	100.005ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.31696843059476704271561854053234584424618331891040519637608370999954682276541
      Line 126, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100004793369 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x13f04b94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100004793369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---