SRAM_CTRL/MAIN Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	42.450s	2.470ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.470s	57.169us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.440s	47.188us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.640s	178.213us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.610s	20.555us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.250s	384.905us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.440s	47.188us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	20.555us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.015m	19.889ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.651m	5.049ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.670m	12.089ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.695m	23.959ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	6.407m	193.885ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.071m	9.434ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	32.330s	11.439ms	1	1	100.00
V2	executable	sram_ctrl_executable	12.200m	46.440ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	26.390s	832.158us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.840m	7.162ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.140s	1.041ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	20.070s	765.740us	1	1	100.00
		sram_ctrl_throughput_w_readback	7.560s	1.488ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.102m	3.202ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.190s	1.355ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	33.140m	257.506ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	15.511us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.410s	28.624us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.410s	28.624us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.470s	57.169us	1	1	100.00
		sram_ctrl_csr_rw	1.440s	47.188us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	20.555us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	26.220us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.470s	57.169us	1	1	100.00
		sram_ctrl_csr_rw	1.440s	47.188us	1	1	100.00
		sram_ctrl_csr_aliasing	1.610s	20.555us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	26.220us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	31.570s	16.005ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.610s	2.249us	0	1	0.00
		sram_ctrl_tl_intg_err	2.480s	110.462us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.610s	2.249us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.480s	110.462us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.102m	3.202ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.102m	3.202ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.440s	47.188us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	12.200m	46.440ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	12.200m	46.440ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	12.200m	46.440ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	32.330s	11.439ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.620s	680.845us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	31.570s	16.005ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.290s	696.429us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	42.450s	2.470ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	42.450s	2.470ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	12.200m	46.440ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.610s	2.249us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	32.330s	11.439ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.610s	2.249us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.610s	2.249us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	42.450s	2.470ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.610s	2.249us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	14.460s	1.223ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.26973314813644829834615870373102063453748365272658864821188904755543077885019
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 696429154 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x5a) != exp (0x6a)
        UVM_INFO @ 696429154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.39469393225573187877233425993658759425668820350099512861472664671772375500994
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   2249304 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   2249304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---