SRAM_CTRL/RET Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	6.520s	421.216us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.480s	20.812us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.600s	14.833us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.050s	44.651us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.550s	22.631us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.780s	39.878us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.600s	14.833us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	22.631us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.920s	2.726ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.890s	164.435us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.208m	19.494ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.031m	11.062ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.310s	701.515us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.923m	7.018ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.400s	241.784us	1	1	100.00
V2	executable	sram_ctrl_executable	4.725m	5.805ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.540s	644.601us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.073m	24.117ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.260s	202.588us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	18.710s	130.768us	1	1	100.00
		sram_ctrl_throughput_w_readback	24.080s	189.525us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.961m	21.112ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.830s	54.887us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	29.260m	51.182ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.540s	33.310us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.980s	295.162us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.980s	295.162us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.480s	20.812us	1	1	100.00
		sram_ctrl_csr_rw	1.600s	14.833us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	22.631us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	30.867us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.480s	20.812us	1	1	100.00
		sram_ctrl_csr_rw	1.600s	14.833us	1	1	100.00
		sram_ctrl_csr_aliasing	1.550s	22.631us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.700s	30.867us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.070s	4.103ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.430s	6.437us	0	1	0.00
		sram_ctrl_tl_intg_err	2.990s	1.799ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.430s	6.437us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.990s	1.799ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.961m	21.112ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.961m	21.112ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.600s	14.833us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.725m	5.805ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.725m	5.805ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.725m	5.805ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.400s	241.784us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.140s	30.201us	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.070s	4.103ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.970s	109.198us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	6.520s	421.216us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	6.520s	421.216us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.725m	5.805ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.430s	6.437us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.400s	241.784us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.430s	6.437us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.430s	6.437us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	6.520s	421.216us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.430s	6.437us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.973m	1.291ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.22992891080363037324597147753942896482693409644278380866731595127623572372431
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  30200686 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  30200686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.73920651195782599533044522126266466570965730942377732810993987686232380328120
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6437478 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6437478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---