UART Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: 841f73f

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.980s	536.268us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.500s	56.643us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.370s	40.884us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.410s	61.753us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.520s	14.647us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.550s	18.297us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.370s	40.884us	1	1	100.00
		uart_csr_aliasing	1.520s	14.647us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.107m	72.825ms	1	1	100.00
V2	parity	uart_smoke	1.980s	536.268us	1	1	100.00
		uart_tx_rx	1.107m	72.825ms	1	1	100.00
V2	parity_error	uart_intr	7.960s	20.971ms	1	1	100.00
		uart_rx_parity_err	32.950s	34.282ms	1	1	100.00
V2	watermark	uart_tx_rx	1.107m	72.825ms	1	1	100.00
		uart_intr	7.960s	20.971ms	1	1	100.00
V2	fifo_full	uart_fifo_full	13.140s	18.403ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	32.920s	65.239ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	18.130s	17.625ms	1	1	100.00
V2	rx_frame_err	uart_intr	7.960s	20.971ms	1	1	100.00
V2	rx_break_err	uart_intr	7.960s	20.971ms	1	1	100.00
V2	rx_timeout	uart_intr	7.960s	20.971ms	1	1	100.00
V2	perf	uart_perf	2.580m	31.633ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.570s	29.525us	1	1	100.00
V2	line_loopback	uart_loopback	1.570s	29.525us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	46.150s	88.224ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.210s	3.611ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	13.190s	6.129ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.480s	3.446ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.714m	125.706ms	1	1	100.00
V2	stress_all	uart_stress_all	9.445m	220.873ms	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	84.298us	1	1	100.00
V2	intr_test	uart_intr_test	1.420s	13.375us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.520s	127.779us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.520s	127.779us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.500s	56.643us	1	1	100.00
		uart_csr_rw	1.370s	40.884us	1	1	100.00
		uart_csr_aliasing	1.520s	14.647us	1	1	100.00
		uart_same_csr_outstanding	1.520s	23.479us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.500s	56.643us	1	1	100.00
		uart_csr_rw	1.370s	40.884us	1	1	100.00
		uart_csr_aliasing	1.520s	14.647us	1	1	100.00
		uart_same_csr_outstanding	1.520s	23.479us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.770s	105.635us	1	1	100.00
		uart_tl_intg_err	1.690s	227.055us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.690s	227.055us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	10.600s	7.429ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00