CHIP Simulation Results

Monday April 28 2025 17:09:10 UTC

GitHub Revision: `841f73f`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.078m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.078m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	20.027s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.546m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	11.189s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.979m	6.624ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.979m	6.624ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.979m	6.624ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	1.619m		0	1	0.00
		chip_sw_example_manufacturer	32.540s		0	1	0.00
		chip_sw_example_concurrency	3.533m	4.601ms	1	1	100.00
		chip_sw_uart_smoketest_signed	17.589s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.210s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	15.670s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	15.670s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.710s	12.319us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	41.053s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.206m	6.676ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.710m	3.782ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.306m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.045m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.063m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.274m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.920s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.920s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.089m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.080m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.240m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.240m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.050m	3.647ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.115m	3.654ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.760m	15.507ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	13.025s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.934s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	21.780m	34.073ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.739m	5.646ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	20.450m	18.022ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	20.450m	18.022ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.854s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.936s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	11.936s		0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	17.498s		0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.604m	4.330ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.324m	4.597ms	1	1	100.00
		chip_sw_aes_idle	4.106m	4.459ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.332m	4.954ms	1	1	100.00
		chip_sw_kmac_idle	3.548m	4.692ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.498s		0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.159s		0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.124s		0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.772s		0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.944s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.232s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.142s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.133s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.124s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.307s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.780s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.944s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.232s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.142s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.133s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.124s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.307s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.780s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.481s		0	1	0.00
		chip_sw_aes_enc_jitter_en	51.570s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	49.340s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.740s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	44.750s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.152s		0	1	0.00
		chip_sw_clkmgr_jitter	3.899m	3.420ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.615m	4.798ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.090s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	53.320s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	48.260s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	52.850s	10.260us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	52.840s	10.360us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	50.650s	10.200us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.507s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.116s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.732s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.818s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	4.236m	3.842ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.431m	13.901ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	11.936s		0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	14.313s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.431m	13.901ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.825s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	16.646s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.668s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	17.137s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.342s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	4.236m	3.842ms	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.760m	15.507ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	22.622m	20.015ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.391m	9.561ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.404m	30.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.040m	4.290ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	4.236m	3.842ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	12.238s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.680s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	4.236m	3.842ms	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	10.672s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.404m	30.016ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.232s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.615s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.664s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.595s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.285s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.676s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.680s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.553s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.276m	8.326ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.579s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.950s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.647s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.129s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.617m	8.310ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.370m	12.570ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.655s		0	1	0.00
		chip_prim_tl_access	19.683m	35.983ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.944s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.232s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	15.142s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.133s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.124s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.307s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.780s		0	1	0.00
		chip_rv_dm_lc_disabled	21.780m	34.073ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.025m	4.923ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	51.570s	10.100us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.478m	4.627ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.106m	4.459ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.472m	4.229ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	49.340s	10.120us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.332m	4.954ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.663m	5.438ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.216m	4.520ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	44.750s	10.200us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.617m	8.310ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	44.990s	10.240us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.854m	5.712ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.548m	4.692ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.296s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.296s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	11.766s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.875m	3.636ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	11.616s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.617m	8.310ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.740s	10.380us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.211s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	13.481s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.324m	4.597ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.324m	4.597ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.324m	4.597ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	9.067m	5.547ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.370m	12.570ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.370m	12.570ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.648m	7.208ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.152s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.655s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	4.236m	3.842ms	0	1	0.00
		chip_sw_data_integrity_escalation	2.240m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	9.067m	5.547ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.617m	8.310ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.648m	7.208ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.438m	5.898ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	9.067m	5.547ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.617m	8.310ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.648m	7.208ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.438m	5.898ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.196s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.553s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.579s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.950s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.647s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.129s		0	1	0.00
		chip_sw_lc_ctrl_transition	12.357s		0	1	0.00
		chip_prim_tl_access	19.683m	35.983ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	19.683m	35.983ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.804s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	13.213s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.116s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	13.481s		0	1	0.00
		chip_sw_aes_enc_jitter_en	51.570s	10.100us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	49.340s	10.120us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.740s	10.380us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	44.750s	10.200us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.152s		0	1	0.00
		chip_sw_clkmgr_jitter	3.899m	3.420ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.941m	8.490ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.941m	8.490ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.811m	3.514ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.360m	4.687ms	1	1	100.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.389m	4.249ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.183m	5.271ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.745m	5.274ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.395m	4.308ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.438m	5.898ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	22.622m	20.015ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	22.622m	20.015ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.422m	5.539ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.599m	4.131ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.006m	3.314ms	1	1	100.00
		chip_sw_csrng_smoketest	3.699m	5.125ms	1	1	100.00
		chip_sw_gpio_smoketest	3.675m	4.739ms	1	1	100.00
		chip_sw_hmac_smoketest	3.736m	4.440ms	1	1	100.00
		chip_sw_kmac_smoketest	4.384m	5.801ms	1	1	100.00
		chip_sw_otbn_smoketest	4.990m	5.739ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.818m	4.419ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.136m	4.858ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.357m	4.277ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.345m	5.544ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.781m	4.952ms	1	1	100.00
		chip_sw_uart_smoketest	3.702m	3.477ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	35.404s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	17.589s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	41.053s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.096s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.175m	6.418ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.103m	6.132ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.154m	4.679ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.767m	6.705ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.447s		0	1	0.00
		chip_rv_dm_lc_disabled	21.780m	34.073ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	38.689s		0	1	0.00
		chip_sw_lc_walkthrough_prod	11.744s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	15.269s		0	1	0.00
		chip_sw_lc_walkthrough_rma	12.969s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	21.447s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.570s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.872s		0	1	0.00
		rom_volatile_raw_unlock	10.925s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.298s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.711m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.036m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.452m	3.380ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.452m	3.380ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	15.670s		0	1	0.00
		chip_same_csr_outstanding	15.460s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	15.670s		0	1	0.00
		chip_same_csr_outstanding	15.460s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.581m	536.911us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.440s	12.856us	1	1	100.00
		xbar_smoke_large_delays	4.210m	2.277ms	1	1	100.00
		xbar_smoke_slow_rsp	5.549m	2.114ms	1	1	100.00
		xbar_random_zero_delays	1.338m	47.332us	1	1	100.00
		xbar_random_large_delays	11.073m	5.778ms	1	1	100.00
		xbar_random_slow_rsp	26.752m	10.301ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.804m	249.616us	1	1	100.00
		xbar_error_and_unmapped_addr	45.680s	33.223us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.139m	57.269us	1	1	100.00
		xbar_error_and_unmapped_addr	45.680s	33.223us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.055m	188.448us	1	1	100.00
		xbar_access_same_device_slow_rsp	40.642m	16.025ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.617m	467.626us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.892m	900.596us	1	1	100.00
		xbar_stress_all_with_error	1.302m	80.663us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	26.091m	3.557ms	1	1	100.00
		xbar_stress_all_with_reset_error	5.519m	262.688us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.573s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.618s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.590s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.798s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.799s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.671s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.177s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.890s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.713s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.500s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.495s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.776s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.894s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.997s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.388s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.105s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.868s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.613s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.146s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.656s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.553s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.578s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.678s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.500s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.880s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.664s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.140s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.570s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.963s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.152s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.040s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.964s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.040s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.711s		0	1	0.00
		rom_e2e_asm_init_dev	11.180s		0	1	0.00
		rom_e2e_asm_init_prod	10.821s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.200s		0	1	0.00
		rom_e2e_asm_init_rma	12.502s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.766s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.983s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.959s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.505s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.667m	5.377ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.400m	5.567ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	10.728s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.494s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.164s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.728s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	4.236m	3.842ms	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.091s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.741m	12.436ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.018s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	13.151s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	10.728s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.494s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.164s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.113s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.185s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.914s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.364m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.902m	13.001ms	1	1	100.00
		chip_plic_all_irqs_0	8.624m	5.721ms	1	1	100.00
		chip_plic_all_irqs_10	9.662m	6.755ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.073m	5.966ms	1	1	100.00
		chip_sw_dma_abort	4.258m	4.446ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.148s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.573s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.557s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.657s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.004s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.980s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.495s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.936s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.516s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.588s		0	1	0.00
		chip_sw_mbx_smoketest	4.207m	4.655ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 143 failures:

Test chip_sw_example_rom has 1 failures.

0.chip_sw_example_rom.48068877758751928692819275169576929325792440191458418602402490471298207641482
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:example_test_from_rom_sim_dv' failed; build aborted: Target //sw/device/tests:example_test_from_rom_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:example_test_from_rom_sim_dv (c396ac)
      //hw/top_earlgrey/sw/autogen:top_earlgrey (82d619)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 79.020s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.29366813955373287453453387004598192881014556780866050268963716201151409621483
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (12 packages loaded, 13 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (7141ae)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.334s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.113071393590179810469861026537858285571585187678003389783091352391010586760594
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (a18ecd)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 123.110s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.54850070161126048047876886744207365350965612553092705334671913497218978998232
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (6235d7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 115.462s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.2421434863715290083635726778408745079329976039080739521567872304112145310610
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (d14384)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 114.819s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 138 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.36603328484985859660694282074189516977980439006360949037701164619640502820380
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.109060450001878591921414558042283226213258668350675274585502810788084657907514
    Line 412, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.36635295483463927497407935256504576686765137245592195673530720570689404266263
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.966303436436986132817696708149979044326032359401824014768349128295197393507
    Line 411, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.51296962095331475445520648161908750836687430914415511789566861802694285914735
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.25602518180941480393245598413905904648862725938984578261458427064866372960368
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.2699282425804071278124792457351720325402887968714815606946815240549589507659
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.78455446655127148189854103031234817211660107934746087013829872494615085397922
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_alert_info has 1 failures.

0.chip_sw_rstmgr_alert_info.84113057951369986797507921077083193104438344085601752239230459841429294690940
Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log

  UVM_ERROR @ 30015.646180 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 30000000 ns

  UVM_INFO @ 30015.646180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.87147032777175558328352716447903484924845023295684352301177119977439852627154
Line 485, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20014.844718 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20014.844718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.104802177417147817770574058901061619609642056373430332581760049637265744186096
Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18022.385721 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18022.385721 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.40560930668617012991886769421508088638904984157381107397266387291977308273644
Line 469, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8310.452280 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (54097219547192955832988372699786143260372331080381682111329927887096795339848 [0x7799f0f2cb9ca7dc5dfa528f53867d026a83e6e69504603298551e29d50b9c48] vs 69935752506809967270085584854021411277111472836756127953649060322927002274052 [0x9a9e3bb1831ace9dbd8651cb4c27d492a75f485b7ac476ffdb67480808ec4904])
  UVM_INFO @ 8310.452280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.114852004824039994323740354160991113389716581038218834253138993340736972827399
Line 459, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 8325.911776 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (108215740338311116081403495109115398131912432755272509525127858457050290606121 [0xef3ff040a3fc0f1ce25652bb5305bebfa9cbf6f0b289dc5c206c2077873c5029] vs 66845163952786084156294718133996598021981008268890715560876347700448426495118 [0x93c905a4c619e2b3aad8f0b462953eddb1d989210c35fbafc997691937e48c8e])
  UVM_INFO @ 8325.911776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.10313440678613270197088411206006740048862489972897077572625639889019707628580
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3647.000289 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'heef74a57  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h0  a_user: 'h2696c  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3647.000289 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.48603297804500249650475865864491922831829705863470063583043952251018484002027
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3653.932321 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h32f3453c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h25  a_opcode: 'h1  a_user: 'h248f9  d_param: 'h0  d_source: 'h25  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3653.932321 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.99094958969943426932204213769104970191711481374184805157247031189242174041442
    Line 470, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3842.438574 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:634)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
  UVM_INFO @ 3842.438574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.18604220106590735294306017865416615302822029657702527682306848805502565387018
    Line 461, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3782.413190 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3782.413190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.36050014798931175023299054472343796571803016817901146406911616029747511285751
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3513.684184 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3513.684184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.4681093774120032705815870245340234462595203189564967907637030814906171874043
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5270.880220 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5270.880220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.89471420752004143920586905526718686193938307807672170387383946816157055887609
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@37714) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.108604596717700438352343659227480347088427421030576852507338572395852193209567
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3380.394464 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@37714) { a_addr: 'h2210  a_data: 'h83edd03d  a_mask: 'h1  a_size: 'h1  a_param: 'h0  a_source: 'h75  a_opcode: 'h4  a_user: 'h260e9  d_param: 'h0  d_source: 'h75  d_data: 'h0  d_size: 'h1  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h12a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3380.394464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.34015421332640392101092701828018664636636493579318676059381609139806927662280
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15506.510958 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15506.510958 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.58884773292202014746407388943027044145940290938166963841672784489460325790713
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.112669504867089212453170358804338742319615133528775165226932865948950228589735
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 4446.374184 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 4446.374184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```