DMA Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	267.200us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	356.167us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	362.990us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	33.410us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	69.902us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	7.000s	160.089us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	623.759us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	26.202us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	69.902us	1	1	100.00
		dma_csr_aliasing	7.000s	623.759us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.800m	32.924ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	9.900m	243.241ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	1.667m	34.909ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	31.600m	421.388ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	9.900m	243.241ms	1	1	100.00
V2	dma_abort	dma_abort	17.000s	4.764ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.200m	6.149ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	112.367us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	7.000s	445.955us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	7.000s	445.955us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	33.410us	1	1	100.00
		dma_csr_rw	4.000s	69.902us	1	1	100.00
		dma_csr_aliasing	7.000s	623.759us	1	1	100.00
		dma_same_csr_outstanding	6.000s	236.159us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	33.410us	1	1	100.00
		dma_csr_rw	4.000s	69.902us	1	1	100.00
		dma_csr_aliasing	7.000s	623.759us	1	1	100.00
		dma_same_csr_outstanding	6.000s	236.159us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	29.000s	97.451us	1	1	100.00
		dma_generic_stress	31.600m	421.388ms	1	1	100.00
		dma_handshake_stress	9.900m	243.241ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	320.315us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.450m	6.272ms	1	1	100.00
		dma_longer_transfer	7.000s	1.509ms	1	1	100.00
		TOTAL			21	21	100.00