EDN Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.700s	29.914us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.560s	26.301us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.750s	15.273us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.370s	120.139us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.990s	32.765us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.970s	30.405us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.750s	15.273us	1	1	100.00
		edn_csr_aliasing	1.990s	32.765us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.180s	55.315us	1	1	100.00
V2	csrng_commands	edn_genbits	2.180s	55.315us	1	1	100.00
V2	genbits	edn_genbits	2.180s	55.315us	1	1	100.00
V2	interrupts	edn_intr	1.690s	35.671us	1	1	100.00
V2	alerts	edn_alert	1.870s	48.962us	1	1	100.00
V2	errs	edn_err	2.050s	29.795us	1	1	100.00
V2	disable	edn_disable	1.770s	13.350us	1	1	100.00
		edn_disable_auto_req_mode	1.660s	158.153us	1	1	100.00
V2	stress_all	edn_stress_all	2.910s	122.685us	1	1	100.00
V2	intr_test	edn_intr_test	1.650s	23.246us	1	1	100.00
V2	alert_test	edn_alert_test	1.890s	33.983us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.570s	56.700us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.570s	56.700us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.560s	26.301us	1	1	100.00
		edn_csr_rw	1.750s	15.273us	1	1	100.00
		edn_csr_aliasing	1.990s	32.765us	1	1	100.00
		edn_same_csr_outstanding	1.830s	150.342us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.560s	26.301us	1	1	100.00
		edn_csr_rw	1.750s	15.273us	1	1	100.00
		edn_csr_aliasing	1.990s	32.765us	1	1	100.00
		edn_same_csr_outstanding	1.830s	150.342us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	4.260s	969.289us	1	1	100.00
		edn_tl_intg_err	2.700s	169.253us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.710s	36.539us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.870s	48.962us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.260s	969.289us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.260s	969.289us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.260s	969.289us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.260s	969.289us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.870s	48.962us	1	1	100.00
		edn_sec_cm	4.260s	969.289us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.870s	48.962us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.700s	169.253us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	21.600s	1.258ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00