| V1 |
smoke |
hmac_smoke |
6.090s |
1.203ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
hmac_csr_hw_reset |
1.650s |
42.975us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
hmac_csr_rw |
1.790s |
388.686us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
hmac_csr_bit_bash |
4.630s |
116.154us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
hmac_csr_aliasing |
3.160s |
367.653us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
hmac_csr_mem_rw_with_rand_reset |
11.430s |
1.960ms |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
hmac_csr_rw |
1.790s |
388.686us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.160s |
367.653us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
long_msg |
hmac_long_msg |
13.710s |
584.424us |
1 |
1 |
100.00 |
| V2 |
back_pressure |
hmac_back_pressure |
21.620s |
1.907ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
hmac_test_sha256_vectors |
8.890s |
700.934us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.975m |
49.087ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.112m |
51.853ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
8.520s |
1.047ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.170s |
1.455ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
14.530s |
413.322us |
1 |
1 |
100.00 |
| V2 |
burst_wr |
hmac_burst_wr |
28.470s |
7.491ms |
1 |
1 |
100.00 |
| V2 |
datapath_stress |
hmac_datapath_stress |
4.223m |
2.334ms |
1 |
1 |
100.00 |
| V2 |
error |
hmac_error |
11.490s |
298.345us |
1 |
1 |
100.00 |
| V2 |
wipe_secret |
hmac_wipe_secret |
1.604m |
61.181ms |
1 |
1 |
100.00 |
| V2 |
save_and_restore |
hmac_smoke |
6.090s |
1.203ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
13.710s |
584.424us |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
21.620s |
1.907ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
4.223m |
2.334ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
28.470s |
7.491ms |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
6.343m |
15.370ms |
1 |
1 |
100.00 |
| V2 |
fifo_empty_status_interrupt |
hmac_smoke |
6.090s |
1.203ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
13.710s |
584.424us |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
21.620s |
1.907ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
4.223m |
2.334ms |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.604m |
61.181ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
8.890s |
700.934us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.975m |
49.087ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.112m |
51.853ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
8.520s |
1.047ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.170s |
1.455ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
14.530s |
413.322us |
1 |
1 |
100.00 |
| V2 |
wide_digest_configurable_key_length |
hmac_smoke |
6.090s |
1.203ms |
1 |
1 |
100.00 |
|
|
hmac_long_msg |
13.710s |
584.424us |
1 |
1 |
100.00 |
|
|
hmac_back_pressure |
21.620s |
1.907ms |
1 |
1 |
100.00 |
|
|
hmac_datapath_stress |
4.223m |
2.334ms |
1 |
1 |
100.00 |
|
|
hmac_burst_wr |
28.470s |
7.491ms |
1 |
1 |
100.00 |
|
|
hmac_error |
11.490s |
298.345us |
1 |
1 |
100.00 |
|
|
hmac_wipe_secret |
1.604m |
61.181ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha256_vectors |
8.890s |
700.934us |
1 |
1 |
100.00 |
|
|
hmac_test_sha384_vectors |
6.975m |
49.087ms |
1 |
1 |
100.00 |
|
|
hmac_test_sha512_vectors |
6.112m |
51.853ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac256_vectors |
8.520s |
1.047ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac384_vectors |
9.170s |
1.455ms |
1 |
1 |
100.00 |
|
|
hmac_test_hmac512_vectors |
14.530s |
413.322us |
1 |
1 |
100.00 |
|
|
hmac_stress_all |
6.343m |
15.370ms |
1 |
1 |
100.00 |
| V2 |
stress_all |
hmac_stress_all |
6.343m |
15.370ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
hmac_alert_test |
1.360s |
10.927us |
1 |
1 |
100.00 |
| V2 |
intr_test |
hmac_intr_test |
1.560s |
14.514us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
hmac_tl_errors |
2.430s |
174.480us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
hmac_tl_errors |
2.430s |
174.480us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
hmac_csr_hw_reset |
1.650s |
42.975us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.790s |
388.686us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.160s |
367.653us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.520s |
72.190us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
hmac_csr_hw_reset |
1.650s |
42.975us |
1 |
1 |
100.00 |
|
|
hmac_csr_rw |
1.790s |
388.686us |
1 |
1 |
100.00 |
|
|
hmac_csr_aliasing |
3.160s |
367.653us |
1 |
1 |
100.00 |
|
|
hmac_same_csr_outstanding |
2.520s |
72.190us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
17 |
17 |
100.00 |
| V2S |
tl_intg_err |
hmac_sec_cm |
1.840s |
590.297us |
1 |
1 |
100.00 |
|
|
hmac_tl_intg_err |
3.430s |
773.902us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
hmac_tl_intg_err |
3.430s |
773.902us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
write_config_and_secret_key_during_msg_wr |
hmac_smoke |
6.090s |
1.203ms |
1 |
1 |
100.00 |
| V3 |
stress_reset |
hmac_stress_reset |
2.980s |
154.717us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
hmac_stress_all_with_rand_reset |
1.537m |
29.457ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
2 |
2 |
100.00 |
|
Unmapped tests |
hmac_directed |
1.800s |
11.369us |
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
28 |
28 |
100.00 |