I2C Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: `e07399c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.090s	1.505ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	15.270s	3.952ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.740s	60.706us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.660s	21.042us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.090s	545.736us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.260s	180.962us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.280s	40.553us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.660s	21.042us	1	1	100.00
		i2c_csr_aliasing	2.260s	180.962us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.610s	675.809us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	13.310m	61.469ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	2.530m	18.906ms	1	1	100.00
V2	host_override	i2c_host_override	1.560s	28.793us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	52.070s	36.169ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	36.090s	4.568ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.850s	126.140us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.160s	244.463us	1	1	100.00
		i2c_host_fifo_reset_rx	6.030s	291.320us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.962m	12.134ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.530s	4.004ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.920s	862.726us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.270s	2.267ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	20.476m	61.080ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.250s	4.628ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	36.930s	4.826ms	1	1	100.00
		i2c_target_intr_smoke	5.070s	4.971ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.920s	599.075us	1	1	100.00
		i2c_target_fifo_reset_tx	2.310s	471.437us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.051m	35.473ms	1	1	100.00
		i2c_target_stress_rd	36.930s	4.826ms	1	1	100.00
		i2c_target_intr_stress_wr	27.030s	9.032ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.630s	1.497ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	12.230s	4.141ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.160s	922.975us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.840s	613.460us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.260s	963.671us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.270s	702.095us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.530m	18.906ms	1	1	100.00
		i2c_host_perf_precise	39.020s	6.455ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.530s	4.004ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.040s	217.327us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.940s	1.622ms	1	1	100.00
		i2c_target_nack_acqfull_addr	3.370s	2.225ms	1	1	100.00
		i2c_target_nack_txstretch	2.040s	636.840us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.100s	2.365ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.430s	6.549ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.900s	39.754us	1	1	100.00
V2	intr_test	i2c_intr_test	1.590s	44.565us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.610s	117.348us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.610s	117.348us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.740s	60.706us	1	1	100.00
		i2c_csr_rw	1.660s	21.042us	1	1	100.00
		i2c_csr_aliasing	2.260s	180.962us	1	1	100.00
		i2c_same_csr_outstanding	1.940s	538.178us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.740s	60.706us	1	1	100.00
		i2c_csr_rw	1.660s	21.042us	1	1	100.00
		i2c_csr_aliasing	2.260s	180.962us	1	1	100.00
		i2c_same_csr_outstanding	1.940s	538.178us	1	1	100.00
V2		TOTAL			37	38	97.37
V2S	tl_intg_err	i2c_tl_intg_err	2.510s	159.276us	1	1	100.00
		i2c_sec_cm	1.850s	126.497us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.510s	159.276us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	19.850s	2.046ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.830s	100.197us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.810s	1.345ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			46	50	92.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.112972308224237584435851951893012608037573682842053495525970184471776315562184
    Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2045806251 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2045806251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.21573324328587770547940547842679570067654265869538908870794425233486295655638
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1345405539 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1345405539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.54538219714453201113633956812934731942149112625067299090963069910312748263992
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 100197245 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 100197245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.41032675128374008816411765777169341903085944925488463915591264475682327881390
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 862726046 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @41557