KEYMGR Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.330s	568.721us	1	1	100.00
V1	random	keymgr_random	41.090s	6.214ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.730s	73.161us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.580s	36.179us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.950s	878.067us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.080s	201.120us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.170s	71.405us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.580s	36.179us	1	1	100.00
		keymgr_csr_aliasing	4.080s	201.120us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	9.050s	438.656us	1	1	100.00
V2	sideload	keymgr_sideload	2.530s	251.047us	1	1	100.00
		keymgr_sideload_kmac	3.390s	80.131us	1	1	100.00
		keymgr_sideload_aes	4.120s	112.457us	1	1	100.00
		keymgr_sideload_otbn	2.900s	38.291us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.730s	42.438us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	5.470s	344.972us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.930s	262.723us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	6.590s	308.438us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.130s	30.900us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.760s	54.444us	1	1	100.00
V2	stress_all	keymgr_stress_all	5.680s	644.479us	1	1	100.00
V2	intr_test	keymgr_intr_test	1.600s	12.862us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.700s	66.150us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.290s	141.256us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.290s	141.256us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.730s	73.161us	1	1	100.00
		keymgr_csr_rw	1.580s	36.179us	1	1	100.00
		keymgr_csr_aliasing	4.080s	201.120us	1	1	100.00
		keymgr_same_csr_outstanding	2.540s	185.656us	0	1	0.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.730s	73.161us	1	1	100.00
		keymgr_csr_rw	1.580s	36.179us	1	1	100.00
		keymgr_csr_aliasing	4.080s	201.120us	1	1	100.00
		keymgr_same_csr_outstanding	2.540s	185.656us	0	1	0.00
V2		TOTAL			15	16	93.75
V2S	sec_cm_additional_check	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
		keymgr_tl_intg_err	4.620s	179.294us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.460s	276.782us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.460s	276.782us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.460s	276.782us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.460s	276.782us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	7.960s	783.631us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.620s	179.294us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.460s	276.782us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	9.050s	438.656us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	41.090s	6.214ms	1	1	100.00
		keymgr_csr_rw	1.580s	36.179us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	41.090s	6.214ms	1	1	100.00
		keymgr_csr_rw	1.580s	36.179us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	41.090s	6.214ms	1	1	100.00
		keymgr_csr_rw	1.580s	36.179us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.470s	344.972us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.130s	30.900us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.130s	30.900us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	41.090s	6.214ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.790s	198.173us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.260s	574.822us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.470s	344.972us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.260s	574.822us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.260s	574.822us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.260s	574.822us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	4.410s	818.784us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.260s	574.822us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	14.460s	661.704us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_same_csr_outstanding has 1 failures.

    • 0.keymgr_same_csr_outstanding.3967727565174263625255307729104829939768479169097641304163221840656613057441
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
        UVM_ERROR @ 185656398 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
        UVM_INFO @ 185656398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---