KMAC/MASKED Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	32.310s	7.621ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.800s	53.781us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.820s	32.407us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.220s	1.176ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.970s	80.884us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.690s	69.372us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.820s	32.407us	1	1	100.00
		kmac_csr_aliasing	3.970s	80.884us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.800s	16.601us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.080s	39.020us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	12.612m	55.649ms	1	1	100.00
V2	burst_write	kmac_burst_write	2.408m	26.357ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.389m	249.463ms	1	1	100.00
		kmac_test_vectors_sha3_256	26.760s	5.143ms	1	1	100.00
		kmac_test_vectors_sha3_384	21.440s	1.395ms	1	1	100.00
		kmac_test_vectors_sha3_512	16.780m	32.741ms	1	1	100.00
		kmac_test_vectors_shake_128	2.333m	28.698ms	1	1	100.00
		kmac_test_vectors_shake_256	24.036m	21.808ms	1	1	100.00
		kmac_test_vectors_kmac	3.140s	91.338us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.780s	39.763us	1	1	100.00
V2	sideload	kmac_sideload	1.136m	11.025ms	1	1	100.00
V2	app	kmac_app	4.219m	17.586ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	18.640s	4.118ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.111m	15.953ms	1	1	100.00
V2	error	kmac_error	5.005m	73.516ms	1	1	100.00
V2	key_error	kmac_key_error	7.720s	1.199ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	8.130s	291.554us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	9.600s	718.672us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.150s	83.674us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	9.240s	1.224ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.310s	39.082us	1	1	100.00
V2	stress_all	kmac_stress_all	31.300s	3.346ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.560s	47.804us	1	1	100.00
V2	alert_test	kmac_alert_test	1.660s	39.641us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.560s	106.592us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.560s	106.592us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.800s	53.781us	1	1	100.00
		kmac_csr_rw	1.820s	32.407us	1	1	100.00
		kmac_csr_aliasing	3.970s	80.884us	1	1	100.00
		kmac_same_csr_outstanding	2.900s	426.848us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.800s	53.781us	1	1	100.00
		kmac_csr_rw	1.820s	32.407us	1	1	100.00
		kmac_csr_aliasing	3.970s	80.884us	1	1	100.00
		kmac_same_csr_outstanding	2.900s	426.848us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.310s	143.865us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.310s	143.865us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.310s	143.865us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.310s	143.865us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.290s	15.909us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	1.352m	47.685ms	1	1	100.00
		kmac_tl_intg_err	2.850s	83.363us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.850s	83.363us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.310s	39.082us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	32.310s	7.621ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.136m	11.025ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.310s	143.865us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.352m	47.685ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.352m	47.685ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.352m	47.685ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	32.310s	7.621ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.310s	39.082us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.352m	47.685ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.722m	12.319ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	32.310s	7.621ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	46.210s	9.780ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.87454642502859999558367575598572507541997701418323220871790704569493847067663
      Line 140, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9779896232 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 9779896232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.37871678047444698244263783757722387384688603486051712522156899848502489717123
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @  15909422 ps: (kmac_csr_assert_fpv.sv:542) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @  15909422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---