KMAC/UNMASKED Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	11.480s	626.859us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.760s	19.448us	1	1	100.00
V1	csr_rw	kmac_csr_rw	2.010s	21.995us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.850s	1.491ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.900s	1.632ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.120s	156.767us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.010s	21.995us	1	1	100.00
		kmac_csr_aliasing	5.900s	1.632ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.660s	14.064us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.160s	18.484us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	28.250m	25.292ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.321m	7.492ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	19.115m	34.896ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.562m	242.850ms	1	1	100.00
		kmac_test_vectors_sha3_384	18.636m	180.880ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.209m	8.915ms	1	1	100.00
		kmac_test_vectors_shake_128	2.117m	28.853ms	1	1	100.00
		kmac_test_vectors_shake_256	3.480m	20.825ms	1	1	100.00
		kmac_test_vectors_kmac	2.860s	111.718us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.660s	201.279us	1	1	100.00
V2	sideload	kmac_sideload	2.970m	9.148ms	1	1	100.00
V2	app	kmac_app	3.484m	28.784ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.000m	4.725ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	32.360s	43.449ms	1	1	100.00
V2	error	kmac_error	2.022m	14.138ms	1	1	100.00
V2	key_error	kmac_key_error	2.160s	2.140ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.000s	195.469us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	20.060s	2.767ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	15.920s	1.730ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	36.610s	14.992ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	14.120s	1.023ms	1	1	100.00
V2	stress_all	kmac_stress_all	3.180m	21.797ms	1	1	100.00
V2	intr_test	kmac_intr_test	2.170s	18.111us	1	1	100.00
V2	alert_test	kmac_alert_test	1.870s	15.007us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.720s	35.693us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.720s	35.693us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.760s	19.448us	1	1	100.00
		kmac_csr_rw	2.010s	21.995us	1	1	100.00
		kmac_csr_aliasing	5.900s	1.632ms	1	1	100.00
		kmac_same_csr_outstanding	2.140s	283.796us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.760s	19.448us	1	1	100.00
		kmac_csr_rw	2.010s	21.995us	1	1	100.00
		kmac_csr_aliasing	5.900s	1.632ms	1	1	100.00
		kmac_same_csr_outstanding	2.140s	283.796us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.540s	629.340us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.540s	629.340us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.540s	629.340us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.540s	629.340us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.510s	71.168us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	15.670s	2.288ms	1	1	100.00
		kmac_tl_intg_err	4.340s	232.050us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.340s	232.050us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	14.120s	1.023ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	11.480s	626.859us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.970m	9.148ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.540s	629.340us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	15.670s	2.288ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	15.670s	2.288ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	15.670s	2.288ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	11.480s	626.859us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	14.120s	1.023ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	15.670s	2.288ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.406m	59.600ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	11.480s	626.859us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	8.100s	347.539us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.7757906359306853576871157031462798860247940188361675322637002638829224804848
      Line 102, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 347538508 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 347538508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.71948274683030289740757744786523282053085040392736836293175667304144437090045
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  71168150 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  71168150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---