e07399c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 37.000s | 8.209ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 10.000s | 14.113us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 10.000s | 11.371us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 10.000s | 103.969us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 9.000s | 19.671us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 7.000s | 1.714us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 10.000s | 11.371us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 9.000s | 19.671us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 51.000s | 2.632ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 7.000s | 94.604us | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 16.000s | 4.772ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 3.000s | 30.307us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 11.000s | 1.053us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 11.000s | 1.053us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 10.000s | 14.113us | 1 | 1 | 100.00 |
| mbx_csr_rw | 10.000s | 11.371us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 9.000s | 19.671us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 9.000s | 21.189us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 10.000s | 14.113us | 1 | 1 | 100.00 |
| mbx_csr_rw | 10.000s | 11.371us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 9.000s | 19.671us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 9.000s | 21.189us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 3.000s | 176.470us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 10.000s | 10.784us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.64229176708867776568961187386316762219082177773492994612630305393370533974724
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1052941 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x519e387c a_data = 0x59187489 a_mask = 0x2 a_size = 0x0 a_param = 0x0 a_source = 0x32 a_opcode = Invalid, value: 5 a_user = 0x24378 d_data = 0x8fec5847 d_size = 0x3 d_param = 0x0 d_source = 0xcb d_opcode = AccessAckData d_error = 0 d_user = 10011101 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1052941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.98835827367146682881849464689816974563123588221357388693934927331711878439312
Line 92, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 10784308 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x9b5b98bc a_data = 0x9a89d95c a_mask = 0x3 a_size = 0x1 a_param = 0x0 a_source = 0x66 a_opcode = Get a_user = 0x2623f d_data = 0xa3b713a1 d_size = 0x2 d_param = 0x0 d_source = 0x51 d_opcode = AccessAck d_error = 0 d_user = 11011101101010 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 10784308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.20713589220105060098139696251747949690985452793052550504210516240483244918425
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1713663 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x2aa6f5a4 a_data = 0xb703b929 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xb7 a_opcode = PutFullData a_user = 0x1a507 d_data = 0xfba1b9fd d_size = 0x1 d_param = 0x0 d_source = 0x8b d_opcode = AccessAckData d_error = 0 d_user = 10010001011010 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1713663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---