OTBN Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	49.744us	1	1	100.00
V1	single_binary	otbn_single	7.000s	12.472us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	36.053us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	43.881us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	35.310us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	42.838us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	8.000s	31.578us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	43.881us	1	1	100.00
		otbn_csr_aliasing	6.000s	42.838us	1	1	100.00
V1	mem_walk	otbn_mem_walk	25.000s	1.199ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	13.000s	498.275us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	23.000s	168.081us	1	1	100.00
V2	multi_error	otbn_multi_err	52.000s	433.838us	1	1	100.00
V2	back_to_back	otbn_multi	27.000s	91.684us	1	1	100.00
V2	stress_all	otbn_stress_all	24.000s	121.312us	1	1	100.00
V2	lc_escalation	otbn_escalate	9.000s	134.998us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	16.288us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	14.000s	48.050us	1	1	100.00
V2	alert_test	otbn_alert_test	6.000s	64.707us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	12.423us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	8.000s	46.947us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	8.000s	46.947us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	36.053us	1	1	100.00
		otbn_csr_rw	6.000s	43.881us	1	1	100.00
		otbn_csr_aliasing	6.000s	42.838us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	34.075us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	36.053us	1	1	100.00
		otbn_csr_rw	6.000s	43.881us	1	1	100.00
		otbn_csr_aliasing	6.000s	42.838us	1	1	100.00
		otbn_same_csr_outstanding	7.000s	34.075us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	8.000s	22.840us	1	1	100.00
		otbn_dmem_err	8.000s	26.844us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	7.000s	27.302us	1	1	100.00
		otbn_controller_ispr_rdata_err	9.000s	13.645us	1	1	100.00
		otbn_mac_bignum_acc_err	12.000s	29.268us	1	1	100.00
		otbn_urnd_err	9.000s	16.339us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	9.000s	35.851us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	9.000s	22.706us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	12.550us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	8.000s	12.194us	0	1	0.00
		otbn_tl_intg_err	40.000s	230.808us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	26.000s	1.098ms	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	prim_count_check	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	49.744us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	26.844us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	8.000s	22.840us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	40.000s	230.808us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	9.000s	134.998us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	8.000s	22.840us	1	1	100.00
		otbn_dmem_err	8.000s	26.844us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.288us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	35.851us	1	1	100.00
		otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	otbn_single	7.000s	12.472us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	8.000s	22.840us	1	1	100.00
		otbn_dmem_err	8.000s	26.844us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.288us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	35.851us	1	1	100.00
		otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	9.000s	134.998us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	8.000s	22.840us	1	1	100.00
		otbn_dmem_err	8.000s	26.844us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	16.288us	1	1	100.00
		otbn_illegal_mem_acc	9.000s	35.851us	1	1	100.00
		otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	7.000s	12.472us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	9.000s	25.837us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	12.141us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	30.000s	113.485us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	30.000s	113.485us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	51.039us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	8.000s	203.317us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	248.581us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	248.581us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	8.000s	9.044us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	7.000s	12.472us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	7.000s	12.472us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	7.000s	12.472us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	27.000s	91.684us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	7.000s	12.472us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	7.000s	12.472us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	11.000s	45.851us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	7.000s	12.472us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	8.000s	12.194us	0	1	0.00
V2S		TOTAL			18	20	90.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.733m	2.853ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	41	95.12

Failure Buckets

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.36064242668427120487227227246349219874956850080437225007425082330409210883087
      Line 111, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 9043883 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @   9043883 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @   9043883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

  • Test otbn_sec_cm has 1 failures.

    • 0.otbn_sec_cm.66361006576041212551904563673302131796391459016385121714755226809082168219846
      Line 84, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 12194397 PS) Assertion tb.dut.ErrBitsKnown_A has failed
        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 12194397 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
        UVM_ERROR @  12194397 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
        UVM_INFO @  12194397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---