ROM_CTRL/64KB Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.260s 573.296us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.230s 550.951us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.110s 215.065us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.970s 888.881us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 7.960s 288.165us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.710s 358.584us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.110s 215.065us 1 1 100.00
rom_ctrl_csr_aliasing 7.960s 288.165us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 8.980s 2.783ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.760s 372.538us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.990s 303.547us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 36.970s 4.505ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 17.160s 4.545ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.270s 287.278us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.580s 299.084us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.580s 299.084us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.230s 550.951us 1 1 100.00
rom_ctrl_csr_rw 7.110s 215.065us 1 1 100.00
rom_ctrl_csr_aliasing 7.960s 288.165us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.220s 958.570us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.230s 550.951us 1 1 100.00
rom_ctrl_csr_rw 7.110s 215.065us 1 1 100.00
rom_ctrl_csr_aliasing 7.960s 288.165us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.220s 958.570us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 40.130s 6.365ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.604m 1.044ms 1 1 100.00
rom_ctrl_tl_intg_err 37.080s 286.838us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.604m 1.044ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.604m 1.044ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.604m 1.044ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.604m 1.044ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.260s 573.296us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.260s 573.296us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.260s 573.296us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 37.080s 286.838us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_kmac_err_chk 17.160s 4.545ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 0 1 0.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 40.130s 6.365ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.604m 1.044ms 1 1 100.00
V2S TOTAL 3 4 75.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.427m 12.020ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 18 19 94.74

Failure Buckets