RV_TIMER Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.410s	29.525us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.380s	40.120us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.460s	35.437us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.550s	1.273ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.660s	35.559us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.610s	130.806us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.460s	35.437us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	35.559us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	5.790s	4.447ms	1	1	100.00
V2	disabled	rv_timer_disabled	1.667m	196.088ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	3.278m	143.607ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	3.278m	143.607ms	1	1	100.00
V2	stress	rv_timer_stress_all	7.326m	748.033ms	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.620s	16.396us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.260s	117.578us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.260s	117.578us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.380s	40.120us	1	1	100.00
		rv_timer_csr_rw	1.460s	35.437us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	35.559us	1	1	100.00
		rv_timer_same_csr_outstanding	1.590s	42.587us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.380s	40.120us	1	1	100.00
		rv_timer_csr_rw	1.460s	35.437us	1	1	100.00
		rv_timer_csr_aliasing	1.660s	35.559us	1	1	100.00
		rv_timer_same_csr_outstanding	1.590s	42.587us	1	1	100.00
V2		TOTAL			7	7	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.960s	197.035us	1	1	100.00
		rv_timer_tl_intg_err	1.880s	43.605us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.880s	43.605us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	27.260s	52.534ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			16	16	100.00