SRAM_CTRL/MAIN Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: e07399c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	3.700s	372.443us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	46.052us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.660s	13.250us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.100s	157.375us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.820s	48.439us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.460s	719.884us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.660s	13.250us	1	1	100.00
		sram_ctrl_csr_aliasing	1.820s	48.439us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.630m	21.886ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.077m	38.337ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.131m	2.022ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.258m	22.781ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	10.800m	181.390ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.608m	11.418ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.350s	1.003ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.618m	67.040ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	17.700s	6.618ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.466m	77.828ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.210s	702.888us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	37.420s	811.600us	1	1	100.00
		sram_ctrl_throughput_w_readback	5.810s	962.037us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.450m	24.980ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.380s	360.854us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.227h	1.071s	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.690s	28.615us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.010s	112.691us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.010s	112.691us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	46.052us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	13.250us	1	1	100.00
		sram_ctrl_csr_aliasing	1.820s	48.439us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.470s	118.038us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	46.052us	1	1	100.00
		sram_ctrl_csr_rw	1.660s	13.250us	1	1	100.00
		sram_ctrl_csr_aliasing	1.820s	48.439us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.470s	118.038us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	36.140s	29.428ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	3.278us	0	1	0.00
		sram_ctrl_tl_intg_err	2.850s	299.004us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	3.278us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.850s	299.004us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.450m	24.980ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.450m	24.980ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.660s	13.250us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.618m	67.040ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.618m	67.040ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.618m	67.040ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.350s	1.003ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.470s	707.170us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	36.140s	29.428ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.680s	2.658ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	3.700s	372.443us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	3.700s	372.443us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.618m	67.040ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	3.278us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.350s	1.003ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	3.278us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	3.278us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	3.700s	372.443us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	3.278us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	59.050s	25.349ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.60677015377373409094787946982314223998130341580362675434987787559727366383850
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3278047 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3278047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---