SRAM_CTRL/RET Simulation Results

Tuesday April 29 2025 17:07:08 UTC

GitHub Revision: `e07399c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.260s	86.063us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	50.922us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.560s	20.612us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.520s	346.974us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.580s	18.958us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.180s	48.134us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.560s	20.612us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	18.958us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.680s	659.558us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.350s	87.687us	1	1	100.00
V1		TOTAL			7	8	87.50
V2	multiple_keys	sram_ctrl_multiple_keys	10.383m	57.279ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.260m	26.654ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.360s	1.298ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	3.290m	3.682ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.130s	638.161us	1	1	100.00
V2	executable	sram_ctrl_executable	9.600m	5.565ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.700s	311.865us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.368m	11.870ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	19.680s	234.432us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	13.640s	99.483us	1	1	100.00
		sram_ctrl_throughput_w_readback	23.550s	188.029us	1	1	100.00
V2	regwen	sram_ctrl_regwen	8.447m	23.188ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.660s	74.778us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	17.490m	69.529ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.800s	40.207us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.370s	137.598us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.370s	137.598us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	50.922us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	20.612us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	18.958us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	50.706us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	50.922us	1	1	100.00
		sram_ctrl_csr_rw	1.560s	20.612us	1	1	100.00
		sram_ctrl_csr_aliasing	1.580s	18.958us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.710s	50.706us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.600s	261.580us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.030s	3.122us	0	1	0.00
		sram_ctrl_tl_intg_err	4.020s	945.841us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.030s	3.122us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.020s	945.841us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	8.447m	23.188ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	8.447m	23.188ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.560s	20.612us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	9.600m	5.565ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	9.600m	5.565ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	9.600m	5.565ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.130s	638.161us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.990s	59.388us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.600s	261.580us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.790s	26.710us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.260s	86.063us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.260s	86.063us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	9.600m	5.565ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.030s	3.122us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.130s	638.161us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.030s	3.122us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.030s	3.122us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.260s	86.063us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.030s	3.122us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	33.690s	6.015ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	31	90.32

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4671) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_readback_err has 1 failures.

0.sram_ctrl_readback_err.31814230241710216609232706449622191622039316214708137478185077336196564535674
Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

  UVM_ERROR @  26709598 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4671) { a_addr: 'h2222f034  a_data: 'h64  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd7  a_opcode: 'h1  a_user: 'h268f4  d_param: 'h0  d_source: 'hd7  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  26709598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending 'pend_req[d2h.d_source].pend' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 0.sram_ctrl_sec_cm.98651044155229225477844639688388602224737372433868796456959628780763864791778
    Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending 'pend_req[d2h.d_source].pend'
  UVM_ERROR @   3121927 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
  UVM_INFO @   3121927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 0.sram_ctrl_csr_mem_rw_with_rand_reset.47890327179854548223373244095456502844103710051689651672904227851360726748550
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  48134384 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  48134384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```